add:cache解码模式

fix:OD输出模式时，输出0需要关闭内部上拉，防止无法拉低

bsp/air105/hal/core_flash.c

@@ -27,6 +27,52 @@
 #define __enable_irq()
 #endif
 
+void __FUNC_IN_RAM__ CACHE_EncryptInit(uint8_t *key, uint8_t *iv, uint32_t start, uint32_t end)
+{
+	int i;
+	uint32_t ckey[4];
+	uint32_t civ[4];
+	for(i = 0; i < 4; i++)
+	{
+		ckey[3 - i] = BytesGetBe32(key + i * 4);
+		civ[3 - i] = BytesGetBe32(iv + i * 4);
+	}
+
+	__disable_irq();
+	for (i = 0; i < 5000; i++)
+	{
+		if (CACHE->CACHE_CS & CACHE_IS_BUSY)	//cache正在从Flash中取指
+		{
+			continue;
+		}
+		break;
+	}
+	CACHE->CACHE_CS = 0x00000000 + CACHE_KEY_GEN;	//密钥生成模式
+
+	CACHE->CACHE_I3 = civ[3];
+	CACHE->CACHE_I2 = civ[2];
+	CACHE->CACHE_I1 = civ[1];
+	CACHE->CACHE_I0 = civ[0];
+	CACHE->CACHE_K3 = ckey[3];
+	CACHE->CACHE_K2 = ckey[2];
+	CACHE->CACHE_K1 = ckey[1];
+	CACHE->CACHE_K0 = ckey[0];
+
+	CACHE->CACHE_CS |= CACHE_KEY_GEN_START;
+	for (i = 0; i < 10000; i++)
+	{
+		if((CACHE->CACHE_CS & CACHE_KEY_GEN_START) == 0)
+		{
+		    break;
+		}
+	}
+	CACHE->CACHE_CS = 0;
+	CACHE->CACHE_SADDR = start;
+	CACHE->CACHE_EADDR = end;
+	CACHE->CACHE_CONFIG = 0xA5A50055;
+	__enable_irq();
+}
+
 void __FUNC_IN_RAM__ CACHE_CleanAll(CACHE_TypeDef *Cache)
 {
 	while (Cache->CACHE_CS & CACHE_IS_BUSY);

bsp/air105/hal/core_gpio.c

@@ -152,6 +152,7 @@ void __FUNC_IN_RAM__ GPIO_Config(uint32_t Pin, uint8_t IsInput, uint8_t InitValu
 		prvGPIO_Resource[Port].RegBase->OEN &= ~Pin;
 	}
 	prvGPIO_Resource[Port].ODBitMap &= ~Pin;
+//	DBG("%d, %x, %x, %x",Port, Pin, prvGPIO_Resource[Port].RegBase->OEN,prvGPIO_Resource[Port].RegBase->IODR);
 }
 
 void __FUNC_IN_RAM__ GPIO_ODConfig(uint32_t Pin, uint8_t InitValue)
@@ -164,13 +165,16 @@ void __FUNC_IN_RAM__ GPIO_ODConfig(uint32_t Pin, uint8_t InitValue)
 	if (InitValue)
 	{
 		prvGPIO_Resource[Port].RegBase->OEN |= Pin;
+		prvGPIO_Resource[Port].RegBase->PUE |= Pin;
 	}
 	else
 	{
+		prvGPIO_Resource[Port].RegBase->PUE &= ~Pin;
 		prvGPIO_Resource[Port].RegBase->BSRR |= (Pin << 16);
 		prvGPIO_Resource[Port].RegBase->OEN &= ~Pin;
 	}
 	prvGPIO_Resource[Port].ODBitMap |= Pin;
+//	DBG("%d, %x, %x, %x",Port, Pin, prvGPIO_Resource[Port].RegBase->OEN, prvGPIO_Resource[Port].RegBase->IODR);
 }
 
 void __FUNC_IN_RAM__ GPIO_PullConfig(uint32_t Pin, uint8_t IsPull, uint8_t IsUp)
@@ -271,10 +275,12 @@ void __FUNC_IN_RAM__ GPIO_Output(uint32_t Pin, uint8_t Level)
 	{
 		if (Level)
 		{
+			prvGPIO_Resource[Port].RegBase->PUE |= Pin;
 			prvGPIO_Resource[Port].RegBase->OEN |= Pin;
 		}
 		else
 		{
+			prvGPIO_Resource[Port].RegBase->PUE &= ~Pin;
 			prvGPIO_Resource[Port].RegBase->BSRR |= (Pin << 16);
 			prvGPIO_Resource[Port].RegBase->OEN &= ~Pin;
 		}
@@ -283,7 +289,7 @@ void __FUNC_IN_RAM__ GPIO_Output(uint32_t Pin, uint8_t Level)
 	{
 		prvGPIO_Resource[Port].RegBase->BSRR |= Level?Pin:(Pin << 16);
 	}
-
+//	DBG("%d, %x, %x, %x",Port, Pin, prvGPIO_Resource[Port].RegBase->OEN, prvGPIO_Resource[Port].RegBase->IODR);
 //	DBG("%d, %x, %x, %x",Port, Pin, prvGPIO_Resource[Port].RegBase, prvGPIO_Resource[Port].RegBase->IODR);
 }
 

bsp/air105/hal/core_rng.c

@@ -42,6 +42,10 @@ void RNG_GetData(uint32_t Buf[4])
 		TRNG->RNG_CSR = 0;
 		while(!(TRNG->RNG_CSR & TRNG_RNG_CSR_S128_TRNG0_Mask)){;}
 	}
+	if (TRNG->RNG_CSR & TRNG_RNG_CSR_ATTACK_TRNG0_Mask)
+	{
+		DBG_ERR("rng attacked !");
+	}
 	Buf[0] = TRNG->RNG_DATA[0];
 	Buf[1] = TRNG->RNG_DATA[0];
 	Buf[2] = TRNG->RNG_DATA[0];