wm_internal_fls.c 38 KB

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  1. /**
  2. * @file wm_internal_fls.c
  3. *
  4. * @brief flash Driver Module
  5. *
  6. * @author dave
  7. *
  8. * Copyright (c) 2015 Winner Microelectronics Co., Ltd.
  9. */
  10. #include <stdio.h>
  11. #include <string.h>
  12. #include <stdlib.h>
  13. #include "wm_dbg.h"
  14. #include "wm_mem.h"
  15. #include "list.h"
  16. #include "wm_regs.h"
  17. #include "wm_internal_flash.h"
  18. #include "wm_flash_map.h"
  19. static struct tls_inside_fls *inside_fls = NULL;
  20. // read/write use the same cache, protect by inside_fls->fls_lock
  21. static u8 tls_fls_cache[INSIDE_FLS_SECTOR_SIZE];
  22. /**System parameter, default for 2M flash*/
  23. unsigned int TLS_FLASH_MESH_PARAM_ADDR = (0x81FA000UL);
  24. unsigned int TLS_FLASH_PARAM_DEFAULT = (0x81FB000UL);
  25. unsigned int TLS_FLASH_PARAM1_ADDR = (0x81FC000UL);
  26. unsigned int TLS_FLASH_PARAM2_ADDR = (0x81FD000UL);
  27. unsigned int TLS_FLASH_PARAM_RESTORE_ADDR = (0x81FE000UL);
  28. unsigned int TLS_FLASH_OTA_FLAG_ADDR = (0x81FF000UL);
  29. unsigned int TLS_FLASH_END_ADDR = (0x81FFFFFUL);
  30. static vu32 read_first_value(void)
  31. {
  32. return M32(RSA_BASE_ADDRESS);
  33. }
  34. static void writeEnable(void)
  35. {
  36. M32(HR_FLASH_CMD_ADDR) = 0x6;
  37. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  38. }
  39. unsigned char readRID(void)
  40. {
  41. M32(HR_FLASH_CMD_ADDR) = 0x2c09F;
  42. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  43. return read_first_value() & 0xFF;
  44. }
  45. static void writeBpBit_for_1wreg(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  46. {
  47. int status = 0;
  48. int bpstatus = 0;
  49. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  50. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  51. status = read_first_value() & 0xFF;
  52. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  53. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  54. status |= (read_first_value() & 0xFF) << 8;
  55. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  56. if ((status & 0x407C) != (bpstatus|(cmp<<14)))
  57. {
  58. status = (status & 0xBF83) | bpstatus | (cmp << 14);
  59. /*Write Enable*/
  60. M32(HR_FLASH_CMD_ADDR) = 0x6;
  61. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  62. M32(RSA_BASE_ADDRESS) = status;
  63. M32(HR_FLASH_CMD_ADDR) = 0x1A001;
  64. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  65. }
  66. }
  67. static void writeBpBit_for_2wreg(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  68. {
  69. int status = 0;
  70. int bpstatus = 0;
  71. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  72. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  73. status = read_first_value() & 0xFF;
  74. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  75. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  76. status |= (read_first_value() & 0xFF) << 8;
  77. /*Write Enable*/
  78. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  79. if ((bpstatus != (status & 0x7C)))
  80. {
  81. bpstatus = (status & 0x83) | bpstatus;
  82. M32(HR_FLASH_CMD_ADDR) = 0x6;
  83. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  84. M32(RSA_BASE_ADDRESS) = bpstatus;
  85. M32(HR_FLASH_CMD_ADDR) = 0xA001;
  86. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  87. }
  88. if (((status & 0x4000)>>8) != (cmp << 6))
  89. {
  90. M32(HR_FLASH_CMD_ADDR) = 0x6;
  91. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  92. status = ((status>>8) & 0xBF) | (cmp << 6);
  93. M32(RSA_BASE_ADDRESS) = status;
  94. M32(HR_FLASH_CMD_ADDR) = 0xA031;
  95. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  96. }
  97. }
  98. static void writeESMTBpBit(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  99. {
  100. int status = 0;
  101. int bpstatus = 0;
  102. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  103. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  104. status = read_first_value() & 0xFF;
  105. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  106. status = (status & 0x83) | bpstatus;
  107. /*Write Enable*/
  108. M32(HR_FLASH_CMD_ADDR) = 0x6;
  109. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  110. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  111. status = (status & 0x83) | bpstatus | (cmp << 14);
  112. M32(RSA_BASE_ADDRESS) = status;
  113. M32(HR_FLASH_CMD_ADDR) = 0x0A001;
  114. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  115. M32(HR_FLASH_CMD_ADDR) = 0x0C085;
  116. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  117. status = read_first_value() & 0xFF;
  118. /*Write Enable*/
  119. M32(HR_FLASH_CMD_ADDR) = 0x6;
  120. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  121. status = (status & 0xBF) | (cmp << 6);
  122. M32(RSA_BASE_ADDRESS) = status;
  123. M32(HR_FLASH_CMD_ADDR) = 0x0A0C1;
  124. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  125. }
  126. static int flashunlock(void)
  127. {
  128. switch(readRID())
  129. {
  130. case SPIFLASH_MID_GD:
  131. case SPIFLASH_MID_TSINGTENG:
  132. writeBpBit_for_1wreg(0, 0, 0, 0, 0, 0);
  133. break;
  134. case SPIFLASH_MID_PUYA:
  135. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  136. if (inside_fls->density == 0x100000)/*PUYA 1M Flash use 1 register to set lock/unlock*/
  137. {
  138. writeBpBit_for_1wreg(0, 0, 0, 0, 0, 0);
  139. }
  140. else
  141. {
  142. writeBpBit_for_2wreg(0, 0, 0, 0, 0, 0);
  143. }
  144. break;
  145. case SPIFLASH_MID_XTX:
  146. case SPIFLASH_MID_BOYA:
  147. case SPIFLASH_MID_FUDANMICRO:
  148. case SPIFLASH_MID_XMC:
  149. writeBpBit_for_2wreg(0, 0, 0, 0, 0, 0);
  150. break;
  151. case SPIFLASH_MID_ESMT:
  152. writeESMTBpBit(0, 0, 0, 0, 0, 0);
  153. break;
  154. default:
  155. return -1;
  156. }
  157. return 0;
  158. }
  159. static int flashlock(void)
  160. {
  161. switch(readRID())
  162. {
  163. case SPIFLASH_MID_GD:
  164. case SPIFLASH_MID_TSINGTENG:
  165. writeBpBit_for_1wreg(0, 1, 1, 0, 1, 0);
  166. break;
  167. case SPIFLASH_MID_PUYA:
  168. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  169. if (inside_fls->density == 0x100000) /*PUYA 1M Flash use 1 register to set lock/unlock*/
  170. {
  171. writeBpBit_for_1wreg(0, 1, 1, 0, 1, 0);
  172. }
  173. else
  174. {
  175. writeBpBit_for_2wreg(0, 1, 1, 0, 1, 0);
  176. }
  177. break;
  178. case SPIFLASH_MID_XTX:
  179. case SPIFLASH_MID_BOYA:
  180. case SPIFLASH_MID_FUDANMICRO:
  181. case SPIFLASH_MID_XMC:
  182. writeBpBit_for_2wreg(0, 1, 1, 0, 1, 0);
  183. break;
  184. case SPIFLASH_MID_ESMT:
  185. writeESMTBpBit(0, 1, 1, 0, 1, 0);
  186. break;
  187. default:
  188. return -1;/*do not clear QIO Mode*/
  189. }
  190. return 0;
  191. }
  192. static void writeLbBit_for_1wreg(unsigned int val)
  193. {
  194. int status = 0;
  195. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  196. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  197. status = read_first_value() & 0xFF;
  198. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  199. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  200. status |= (read_first_value() & 0xFF) << 8;
  201. /*Write Enable*/
  202. M32(HR_FLASH_CMD_ADDR) = 0x6;
  203. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  204. status |= (val);
  205. M32(RSA_BASE_ADDRESS) = status;
  206. M32(HR_FLASH_CMD_ADDR) = 0x1A001;
  207. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  208. }
  209. static void writeLbBit_for_2wreg(unsigned int val)
  210. {
  211. int status = 0;
  212. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  213. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  214. status = read_first_value() & 0xFF;
  215. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  216. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  217. status |= (read_first_value() & 0xFF) << 8;
  218. /*Write Enable*/
  219. M32(HR_FLASH_CMD_ADDR) = 0x6;
  220. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  221. status |= (val);
  222. status = (status>>8);
  223. M32(RSA_BASE_ADDRESS) = status;
  224. M32(HR_FLASH_CMD_ADDR) = 0xA031;
  225. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  226. }
  227. static int programSR(unsigned int cmd, unsigned long addr, unsigned char *buf, unsigned int sz)
  228. {
  229. unsigned long base_addr = 0;
  230. unsigned int size = 0;
  231. if (sz > INSIDE_FLS_PAGE_SIZE)
  232. {
  233. sz = INSIDE_FLS_PAGE_SIZE;
  234. }
  235. base_addr = RSA_BASE_ADDRESS;
  236. size = sz;
  237. while(size)
  238. {
  239. M32(base_addr) = *((unsigned long *)buf);
  240. base_addr += 4;
  241. buf += 4;
  242. size -= 4;
  243. }
  244. writeEnable();
  245. M32(HR_FLASH_CMD_ADDR) = cmd | ((sz - 1) << 16);
  246. M32(HR_FLASH_ADDR) = (addr & 0x1FFFFFF);
  247. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  248. return 0;
  249. }
  250. static int programPage (unsigned long adr, unsigned long sz, unsigned char *buf)
  251. {
  252. programSR(0x80009002, adr, buf, sz);
  253. return(0);
  254. }
  255. static int eraseSR(unsigned int cmd, unsigned long addr)
  256. {
  257. /*Write Enable*/
  258. writeEnable();
  259. M32(HR_FLASH_CMD_ADDR) = cmd;
  260. M32(HR_FLASH_ADDR) = (addr & 0x1FFFFFF);
  261. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  262. return 0;
  263. }
  264. static int eraseSector (unsigned long adr)
  265. {
  266. eraseSR(0x80000820, adr);
  267. return (0); // Finished without Errors
  268. }
  269. #if 0
  270. /*only for XT806 c400 flash*/
  271. static int erasePage (unsigned long addr)
  272. {
  273. eraseSR(0x80000881, addr);
  274. return (0); // Finished without Errors
  275. }
  276. #endif
  277. static unsigned int getFlashDensity(void)
  278. {
  279. unsigned char density = 0;
  280. M32(HR_FLASH_CMD_ADDR) = 0x2c09F;
  281. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  282. density = ((read_first_value() & 0xFFFFFF) >> 16) & 0xFF;
  283. // printf("density %x\n", density);
  284. if (density && (density <= 0x21)) /*just limit to (1<<33UL) Byte*/
  285. {
  286. return (1 << density);
  287. }
  288. return 0;
  289. }
  290. int __readByCMD(unsigned char cmd, unsigned long addr, unsigned char *buf, unsigned long sz)
  291. {
  292. int i = 0;
  293. int word = sz / 4;
  294. int byte = sz % 4;
  295. unsigned long addr_read;
  296. if (!(M32(HR_FLASH_CR)&0x1))/*non-QIO mode, only single line command can be used*/
  297. {
  298. if (cmd > 0x0B)
  299. {
  300. cmd = 0x0B;
  301. }
  302. }
  303. switch (cmd)
  304. {
  305. case 0x03:
  306. M32(HR_FLASH_CMD_ADDR) = 0x8000C003 | (((sz - 1) & 0x3FF) << 16);
  307. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  308. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  309. break;
  310. case 0x0B:
  311. if((M32(HR_FLASH_CR) & 0x2) == 0x2)
  312. {
  313. M32(HR_FLASH_CMD_ADDR) = 0xB400C00B | (((sz - 1) & 0x3FF) << 16);
  314. }
  315. else
  316. {
  317. M32(HR_FLASH_CMD_ADDR) = 0xBC00C00B | (((sz - 1) & 0x3FF) << 16);
  318. }
  319. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  320. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  321. break;
  322. case 0xBB:
  323. M32(HR_FLASH_CMD_ADDR) = 0xE400C0BB | (((sz - 1) & 0x3FF) << 16);
  324. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  325. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  326. break;
  327. case 0xEB:
  328. M32(HR_FLASH_CMD_ADDR) = 0xEC00C0EB | (((sz - 1) & 0x3FF) << 16);
  329. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  330. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  331. break;
  332. default:
  333. return -1;
  334. }
  335. // printf("delay delay delay delay\n");
  336. // dumpUint32("readByCMD RSA_BASE_ADDRESS", RSA_BASE_ADDRESS, sz/4);
  337. addr_read = RSA_BASE_ADDRESS;
  338. for(i = 0; i < word; i ++)
  339. {
  340. M32(buf) = M32(addr_read);
  341. buf += 4;
  342. addr_read += 4;
  343. }
  344. if(byte > 0)
  345. {
  346. M32(buf) = M32(addr_read);
  347. buf += 3; //point last byte
  348. byte = 4 - byte;
  349. while(byte)
  350. {
  351. *buf = 0;
  352. buf --;
  353. byte --;
  354. }
  355. }
  356. return 0;
  357. }
  358. /**
  359. * @brief This function is used to read data from the flash.
  360. *
  361. * @param[in] cmd 0xEB in QSPI mode; 0x0b in SPI mode.
  362. * @param[in] addr is byte offset addr for read from the flash.
  363. * @param[in] buf is user for data buffer of flash read
  364. * @param[in] len is byte length for read.
  365. *
  366. * @retval TLS_FLS_STATUS_OK if read sucsess
  367. * @retval TLS_FLS_STATUS_EPERM if inside fls does not initialized.
  368. *
  369. * @note None
  370. */
  371. int readByCMD(unsigned char cmd, unsigned long addr, unsigned char *buf, unsigned long sz)
  372. {
  373. if (inside_fls == NULL)
  374. {
  375. return TLS_FLS_STATUS_EPERM;
  376. }
  377. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  378. __readByCMD(cmd, addr, buf, sz);
  379. tls_os_sem_release(inside_fls->fls_lock);
  380. return TLS_FLS_STATUS_OK;
  381. }
  382. int config_flash_decrypt_param(uint32_t code_decrypt, uint32_t dbus_decrypt, uint32_t data_decrypt)
  383. {
  384. FLASH_ENCRYPT_CTRL_Type encrypt_ctrl;
  385. encrypt_ctrl.w = M32(HR_FLASH_ENCRYPT_CTRL);
  386. encrypt_ctrl.b.code_decrypt = code_decrypt;
  387. encrypt_ctrl.b.dbus_decrypt = dbus_decrypt;
  388. encrypt_ctrl.b.data_decrypt = data_decrypt;
  389. M32(HR_FLASH_ENCRYPT_CTRL) = encrypt_ctrl.w;
  390. return 0;
  391. }
  392. int flashRead(unsigned long addr, unsigned char *buf, unsigned long sz)
  393. {
  394. #define INSIDE_FLS_MAX_RD_SIZE (1024)
  395. unsigned int flash_addr;
  396. unsigned int sz_pagenum = 0;
  397. unsigned int sz_remain = 0;
  398. int i = 0;
  399. int page_offset = addr & (INSIDE_FLS_PAGE_SIZE - 1);
  400. unsigned int max_size = 0;
  401. if ((page_offset == 0)
  402. && (((unsigned int)buf&0x3) == 0)
  403. && ((sz&0x3) == 0))/*Use 4-bytes aligned and buf must be 4 times, sz must be 4 times*/
  404. {
  405. flash_addr = addr;
  406. if (sz >= 512)
  407. {
  408. max_size = INSIDE_FLS_MAX_RD_SIZE;
  409. }
  410. else
  411. {
  412. max_size = INSIDE_FLS_PAGE_SIZE;
  413. }
  414. sz_pagenum = sz / max_size;
  415. sz_remain = sz % max_size;
  416. for (i = 0; i < sz_pagenum; i++)
  417. {
  418. __readByCMD(0xEB, flash_addr, (unsigned char *)buf, max_size);
  419. buf += max_size;
  420. flash_addr += max_size;
  421. }
  422. if (sz_remain)
  423. {
  424. __readByCMD(0xEB, flash_addr, (unsigned char *)buf, sz_remain);
  425. }
  426. }
  427. else
  428. {
  429. char *cache = tls_fls_cache;
  430. // cache = tls_mem_alloc(INSIDE_FLS_PAGE_SIZE);
  431. // if (cache == NULL)
  432. // {
  433. // TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  434. // return TLS_FLS_STATUS_ENOMEM;
  435. // }
  436. flash_addr = addr & ~(INSIDE_FLS_PAGE_SIZE - 1);
  437. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, INSIDE_FLS_PAGE_SIZE);
  438. if (sz > INSIDE_FLS_PAGE_SIZE - page_offset)
  439. {
  440. MEMCPY(buf, cache + page_offset, INSIDE_FLS_PAGE_SIZE - page_offset);
  441. buf += INSIDE_FLS_PAGE_SIZE - page_offset;
  442. flash_addr += INSIDE_FLS_PAGE_SIZE;
  443. sz_pagenum = (sz - (INSIDE_FLS_PAGE_SIZE - page_offset)) / INSIDE_FLS_PAGE_SIZE;
  444. sz_remain = (sz - (INSIDE_FLS_PAGE_SIZE - page_offset)) % INSIDE_FLS_PAGE_SIZE;
  445. for (i = 0; i < sz_pagenum; i++)
  446. {
  447. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, INSIDE_FLS_PAGE_SIZE);
  448. MEMCPY(buf, cache, INSIDE_FLS_PAGE_SIZE);
  449. buf += INSIDE_FLS_PAGE_SIZE;
  450. flash_addr += INSIDE_FLS_PAGE_SIZE;
  451. }
  452. if (sz_remain)
  453. {
  454. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, sz_remain + (4- sz_remain%4));
  455. MEMCPY(buf, cache, sz_remain);
  456. }
  457. }
  458. else
  459. {
  460. MEMCPY(buf, cache + page_offset, sz);
  461. }
  462. // tls_mem_free(cache);
  463. }
  464. return 0;
  465. }
  466. /**
  467. * @brief This function is used to unlock flash protect area [0x0~0x2000].
  468. *
  469. * @param None
  470. *
  471. * @return 0-success,non-zero-failure
  472. *
  473. * @note None
  474. */
  475. int tls_flash_unlock(void)
  476. {
  477. int ret = 0;
  478. if (inside_fls == NULL)
  479. {
  480. return TLS_FLS_STATUS_EPERM;
  481. }
  482. // return flashunlock();
  483. return ret;
  484. }
  485. /**
  486. * @brief This function is used to lock flash protect area [0x0~0x2000].
  487. *
  488. * @param None
  489. *
  490. * @return 0-success,non-zero-failure
  491. *
  492. * @note None
  493. */
  494. int tls_flash_lock(void)
  495. {
  496. int ret = 0;
  497. if (inside_fls == NULL)
  498. {
  499. return TLS_FLS_STATUS_EPERM;
  500. }
  501. // return flashlock();
  502. return ret;
  503. }
  504. /**
  505. * @brief This function is used to semaphore protect.
  506. *
  507. * @param None
  508. *
  509. * @return None
  510. *
  511. * @note None
  512. */
  513. void tls_fls_sem_lock(void)
  514. {
  515. if (inside_fls == NULL)
  516. {
  517. return;
  518. }
  519. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  520. }
  521. /**
  522. * @brief This function is used to semaphore protect cancel.
  523. *
  524. * @param None
  525. *
  526. * @return None
  527. *
  528. * @note None
  529. */
  530. void tls_fls_sem_unlock(void)
  531. {
  532. if (inside_fls == NULL)
  533. {
  534. return;
  535. }
  536. tls_os_sem_release(inside_fls->fls_lock);
  537. }
  538. /**
  539. * @brief This function is used to read the unique id of the internal flash.
  540. *
  541. * @param[out] uuid Specified the address to save the uuid, the length must be greater than or equals to 18 bytes.
  542. *
  543. * @retval TLS_FLS_STATUS_OK if read sucsess
  544. * @retval TLS_FLS_STATUS_EIO if read fail
  545. *
  546. * @note The uuid's length must be greater than or equals to 18 bytes.
  547. */
  548. int tls_fls_read_unique_id(unsigned char *uuid)
  549. {
  550. unsigned int value = 0;
  551. unsigned int addr_read = 0;
  552. int i = 0;
  553. int len;
  554. unsigned char FLASH_BUF[20];
  555. unsigned char *addr = &FLASH_BUF[0];
  556. int dumy_bytes = 0;
  557. int uni_bytes = 0;
  558. unsigned char rid;
  559. int word;
  560. int byte;
  561. if (inside_fls == NULL)
  562. {
  563. return TLS_FLS_STATUS_EPERM;
  564. }
  565. memset(uuid, 0xFF, 18);
  566. rid = readRID();
  567. switch(rid)
  568. {
  569. case SPIFLASH_MID_GD:
  570. case SPIFLASH_MID_PUYA:
  571. case SPIFLASH_MID_TSINGTENG:
  572. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  573. dumy_bytes = 4;
  574. uni_bytes = 16;
  575. break;
  576. case SPIFLASH_MID_WINBOND:
  577. case SPIFLASH_MID_FUDANMICRO:
  578. case SPIFLASH_MID_BOYA:
  579. case SPIFLASH_MID_XMC:
  580. dumy_bytes = 4;
  581. uni_bytes = 8;
  582. break;
  583. case SPIFLASH_MID_ESMT:
  584. case SPIFLASH_MID_XTX:
  585. default:
  586. return -1;
  587. }
  588. uuid[0] = rid;
  589. uuid[1] = (unsigned char)(uni_bytes & 0xFF);
  590. len = dumy_bytes + uni_bytes;
  591. word = len/4;
  592. byte = len%4;
  593. value = 0xC04B|((len-1) << 16);
  594. M32(HR_FLASH_CMD_ADDR) = value;
  595. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  596. addr_read = RSA_BASE_ADDRESS;
  597. for(i = 0;i < word; i ++)
  598. {
  599. M32(addr) = M32(addr_read);
  600. addr += 4;
  601. addr_read += 4;
  602. }
  603. if(byte > 0)
  604. {
  605. M32(addr) = M32(addr_read);
  606. addr += 3; //point last byte
  607. while(byte)
  608. {
  609. *addr = 0;
  610. addr --;
  611. byte --;
  612. }
  613. }
  614. addr = &FLASH_BUF[0];
  615. memcpy(&uuid[2], addr + dumy_bytes, uni_bytes);
  616. return 0;
  617. }
  618. int tls_fls_otp_read(u32 addr, u8 *buf, u32 len)
  619. {
  620. int err;
  621. int i = 0;
  622. int word = len/4;
  623. int byte = len%4;
  624. unsigned long addr_read = 0xBC00C048;
  625. volatile unsigned long value;
  626. unsigned long addr_offset = 0;
  627. unsigned long sz_need = len;
  628. if (inside_fls == NULL)
  629. {
  630. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  631. return TLS_FLS_STATUS_EPERM;
  632. }
  633. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  634. if(buf)
  635. {
  636. addr_offset = addr % 16;
  637. sz_need = (addr_offset + len + 16) / 16 * 16;
  638. addr = addr / 16 * 16;
  639. }
  640. M32(HR_FLASH_CMD_ADDR) = addr_read|(((sz_need-1)&0x3FF)<<16);
  641. M32(HR_FLASH_ADDR) = (addr&0x1FFFFFF);
  642. M32(HR_FLASH_CMD_START) = tls_reg_read32(HR_FLASH_CMD_START) | CMD_START_Msk;
  643. if(buf)
  644. {
  645. addr_read = RSA_BASE_ADDRESS + (addr_offset / 4 * 4);
  646. i = (4 - addr_offset % 4) % 4;
  647. if(i > len)
  648. {
  649. byte = len;
  650. }
  651. else
  652. {
  653. byte = i;
  654. }
  655. if(byte)
  656. {
  657. value = M32(addr_read);
  658. memcpy(buf, ((char *)&value) + 4 - i, byte);
  659. addr_read += 4;
  660. buf += byte;
  661. }
  662. word = (len - byte) / 4;
  663. for(i = 0;i < word; i ++)
  664. {
  665. value = M32(addr_read);
  666. memcpy(buf, (char*)&value, 4);
  667. buf += 4;
  668. addr_read += 4;
  669. }
  670. byte = (len - byte) % 4;
  671. if(byte > 0)
  672. {
  673. value = M32(addr_read);
  674. memcpy(buf, (char *)&value, byte);
  675. }
  676. }
  677. err = TLS_FLS_STATUS_OK;
  678. tls_os_sem_release(inside_fls->fls_lock);
  679. return err;
  680. }
  681. int tls_fls_otp_write(u32 addr, u8 *buf, u32 len)
  682. {
  683. int ret = 0;
  684. unsigned int erasecmd = 0x80000844;
  685. unsigned int writecmd = 0x80009042;
  686. uint32_t eraseAddr = 0;
  687. uint16_t eraseSize = 0;
  688. uint16_t pageSize = 0;
  689. int l = 0;
  690. unsigned char *backbuf = NULL;
  691. unsigned long size = 0;
  692. unsigned long p = 0;
  693. unsigned char *q = NULL;
  694. if (!buf)
  695. {
  696. return TLS_FLS_STATUS_EINVAL;
  697. }
  698. if (inside_fls == NULL)
  699. {
  700. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  701. return TLS_FLS_STATUS_EPERM;
  702. }
  703. eraseSize = inside_fls->OTPWRParam.eraseSize;
  704. pageSize = inside_fls->OTPWRParam.pageSize;
  705. if (eraseSize == 0 || pageSize == 0)
  706. {
  707. TLS_DBGPRT_ERR("flash type is not supported!\n");
  708. return TLS_FLS_STATUS_ENOSUPPORT;
  709. }
  710. eraseAddr = addr & ~(eraseSize - 1);
  711. if(addr < eraseAddr || len > eraseSize - (addr - eraseAddr))
  712. {
  713. return TLS_FLS_STATUS_EINVAL;
  714. }
  715. TLS_DBGPRT_INFO("addr 0x%x, eraseAddr 0x%x, eraseSize 0x%x, pageSize 0x%x\n", addr, eraseAddr, eraseSize, pageSize);
  716. backbuf = tls_mem_alloc(eraseSize);
  717. if (!backbuf)
  718. {
  719. ret = TLS_FLS_STATUS_ENOMEM;
  720. goto out;
  721. }
  722. p = eraseAddr;
  723. q = backbuf;
  724. size = eraseSize;
  725. while(size > 0)
  726. {
  727. l = size > pageSize ? pageSize : size;
  728. if(tls_fls_otp_read(p, q, l) != TLS_FLS_STATUS_OK)
  729. {
  730. ret = TLS_FLS_STATUS_EPERM;
  731. goto out;
  732. }
  733. q += l;
  734. p += l;
  735. size -= l;
  736. }
  737. eraseSR(erasecmd, eraseAddr);
  738. memcpy(backbuf + (addr - eraseAddr), buf, len);
  739. p = eraseAddr;
  740. q = backbuf;
  741. size = eraseSize;
  742. while(size > 0)
  743. {
  744. l = size > pageSize ? pageSize : size;
  745. programSR(writecmd, p, q, l);
  746. q += l;
  747. p += l;
  748. size -= l;
  749. }
  750. out:
  751. if(backbuf)
  752. tls_mem_free(backbuf);
  753. return ret;
  754. }
  755. int tls_fls_otp_lock(void)
  756. {
  757. if (inside_fls == NULL)
  758. {
  759. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  760. return TLS_FLS_STATUS_EPERM;
  761. }
  762. switch(inside_fls->flashid)
  763. {
  764. case SPIFLASH_MID_GD:
  765. case SPIFLASH_MID_TSINGTENG:
  766. writeLbBit_for_1wreg((1<<10));
  767. break;
  768. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  769. writeLbBit_for_1wreg((7<<11));
  770. break;
  771. case SPIFLASH_MID_FUDANMICRO:
  772. writeLbBit_for_2wreg((1<<10));
  773. break;
  774. case SPIFLASH_MID_BOYA:
  775. case SPIFLASH_MID_XMC:
  776. case SPIFLASH_MID_WINBOND:
  777. case SPIFLASH_MID_PUYA:
  778. writeLbBit_for_2wreg((7<<11));
  779. break;
  780. case SPIFLASH_MID_XTX:
  781. case SPIFLASH_MID_ESMT:
  782. default:
  783. TLS_DBGPRT_ERR("flash is not supported!\n");
  784. return TLS_FLS_STATUS_ENOSUPPORT;
  785. }
  786. return 0;
  787. }
  788. /**
  789. * @brief This function is used to read data from the flash.
  790. *
  791. * @param[in] addr is byte offset addr for read from the flash.
  792. * @param[in] buf is user for data buffer of flash read
  793. * @param[in] len is byte length for read.
  794. *
  795. * @retval TLS_FLS_STATUS_OK if read sucsess
  796. * @retval TLS_FLS_STATUS_EIO if read fail
  797. *
  798. * @note None
  799. */
  800. int tls_fls_read(u32 addr, u8 *buf, u32 len)
  801. {
  802. int err;
  803. if (inside_fls == NULL)
  804. {
  805. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  806. return TLS_FLS_STATUS_EPERM;
  807. }
  808. if (((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= inside_fls->density) || (len == 0) || (buf == NULL))
  809. {
  810. return TLS_FLS_STATUS_EINVAL;
  811. }
  812. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  813. flashRead(addr, buf, len);
  814. err = TLS_FLS_STATUS_OK;
  815. tls_os_sem_release(inside_fls->fls_lock);
  816. return err;
  817. }
  818. /**
  819. * @brief This function is used to write data to the flash.
  820. *
  821. * @param[in] addr is byte offset addr for write to the flash
  822. * @param[in] buf is the data buffer want to write to flash
  823. * @param[in] len is the byte length want to write
  824. *
  825. * @retval TLS_FLS_STATUS_OK if write flash success
  826. * @retval TLS_FLS_STATUS_EPERM if flash struct point is null
  827. * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed
  828. * @retval TLS_FLS_STATUS_EINVAL if argument is invalid
  829. * @retval TLS_FLS_STATUS_EIO if io error
  830. *
  831. * @note None
  832. */
  833. int tls_fls_write(u32 addr, u8 *buf, u32 len)
  834. {
  835. u8 *cache = tls_fls_cache;
  836. unsigned int secpos;
  837. unsigned int secoff;
  838. unsigned int secremain;
  839. unsigned int i;
  840. unsigned int offaddr;
  841. if (inside_fls == NULL)
  842. {
  843. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  844. return TLS_FLS_STATUS_EPERM;
  845. }
  846. if (((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= inside_fls->density) || (len == 0) || (buf == NULL))
  847. {
  848. return TLS_FLS_STATUS_EINVAL;
  849. }
  850. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  851. // cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  852. // if (cache == NULL)
  853. // {
  854. // tls_os_sem_release(inside_fls->fls_lock);
  855. // TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  856. // return TLS_FLS_STATUS_ENOMEM;
  857. // }
  858. offaddr = addr & (INSIDE_FLS_BASE_ADDR - 1); //Offset of 0X08000000
  859. secpos = offaddr / INSIDE_FLS_SECTOR_SIZE; //Section addr
  860. secoff = (offaddr % INSIDE_FLS_SECTOR_SIZE); //Offset in section
  861. secremain = INSIDE_FLS_SECTOR_SIZE - secoff; // 扇区剩余空间大小
  862. if(len <= secremain)
  863. {
  864. secremain = len; //Not bigger with remain size in section
  865. }
  866. while (1)
  867. {
  868. flashRead(secpos * INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE);
  869. eraseSector(secpos * INSIDE_FLS_SECTOR_SIZE);
  870. for (i = 0; i < secremain; i++) // 复制
  871. {
  872. cache[i + secoff] = buf[i];
  873. }
  874. for (i = 0; i < (INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE); i++)
  875. {
  876. programPage(secpos * INSIDE_FLS_SECTOR_SIZE + i * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE, &cache[i * INSIDE_FLS_PAGE_SIZE]); //Write
  877. }
  878. if(len == secremain)
  879. {
  880. break; // 写入结束了
  881. }
  882. else // 写入未结束
  883. {
  884. secpos++; // 扇区地址增1
  885. secoff = 0; // 偏移位置为0
  886. buf += secremain; // 指针偏移
  887. len -= secremain;
  888. if(len > (INSIDE_FLS_SECTOR_SIZE))
  889. {
  890. secremain = INSIDE_FLS_SECTOR_SIZE; // 下一个扇区还是写不完
  891. }
  892. else
  893. {
  894. secremain = len; //Next section will finish
  895. }
  896. }
  897. }
  898. // tls_mem_free(cache);
  899. tls_os_sem_release(inside_fls->fls_lock);
  900. return TLS_FLS_STATUS_OK;
  901. }
  902. /**
  903. * @brief This function is used to write data into the flash without erase.
  904. *
  905. * @param[in] addr Specifies the starting address to write to
  906. * @param[in] buf Pointer to a byte array that is to be written
  907. * @param[in] len Specifies the length of the data to be written
  908. *
  909. * @retval TLS_FLS_STATUS_OK if write flash success
  910. * @retval TLS_FLS_STATUS_EPERM if flash struct point is null
  911. * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed
  912. * @retval TLS_FLS_STATUS_EINVAL if argument is invalid
  913. *
  914. * @note Erase action should be excuted by API tls_fls_erase in user layer.
  915. */
  916. int tls_fls_write_without_erase(u32 addr, u8 *buf, u32 len)
  917. {
  918. u8 *cache;
  919. unsigned int pagepos;
  920. unsigned int pageoff;
  921. unsigned int pageremain;
  922. unsigned int i;
  923. unsigned int offaddr;
  924. if (inside_fls == NULL)
  925. {
  926. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  927. return TLS_FLS_STATUS_EPERM;
  928. }
  929. if (((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= inside_fls->density) || (len == 0) || (buf == NULL))
  930. {
  931. return TLS_FLS_STATUS_EINVAL;
  932. }
  933. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  934. cache = tls_mem_alloc(INSIDE_FLS_PAGE_SIZE);
  935. if (cache == NULL)
  936. {
  937. tls_os_sem_release(inside_fls->fls_lock);
  938. TLS_DBGPRT_ERR("allocate page cache memory fail!\n");
  939. return TLS_FLS_STATUS_ENOMEM;
  940. }
  941. offaddr = addr & (INSIDE_FLS_BASE_ADDR - 1); //Offset of 0X08000000
  942. pagepos = offaddr / INSIDE_FLS_PAGE_SIZE; //Page addr
  943. pageoff = (offaddr % INSIDE_FLS_PAGE_SIZE); //Offset in page
  944. pageremain = INSIDE_FLS_PAGE_SIZE - pageoff; // size remained in one page
  945. if(len <= pageremain)
  946. {
  947. pageremain = len; //Not bigger with remain size in one page
  948. }
  949. flashRead(pagepos * INSIDE_FLS_PAGE_SIZE, cache, INSIDE_FLS_PAGE_SIZE);
  950. while (1)
  951. {
  952. for (i = 0; i < pageremain; i++)
  953. {
  954. cache[i + pageoff] = buf[i];
  955. }
  956. programPage(pagepos * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE, &cache[0]); //Write
  957. if(len == pageremain)// page program over
  958. {
  959. break;
  960. }
  961. else
  962. {
  963. pagepos++; // next page
  964. pageoff = 0; // page offset set to zero
  965. buf += pageremain; // buffer modified
  966. len -= pageremain; // len decrease
  967. if(len > (INSIDE_FLS_PAGE_SIZE))
  968. {
  969. pageremain = INSIDE_FLS_PAGE_SIZE; // size next to write
  970. }
  971. else
  972. {
  973. pageremain = len; //last data to write
  974. flashRead(pagepos * INSIDE_FLS_PAGE_SIZE, cache, INSIDE_FLS_PAGE_SIZE);
  975. }
  976. }
  977. }
  978. tls_mem_free(cache);
  979. tls_os_sem_release(inside_fls->fls_lock);
  980. return TLS_FLS_STATUS_OK;
  981. }
  982. /**
  983. * @brief This function is used to erase the appoint sector
  984. *
  985. * @param[in] sector sector num of the flash, 4K byte a sector
  986. *
  987. * @retval TLS_FLS_STATUS_OK if read sucsess
  988. * @retval other if read fail
  989. *
  990. * @note None
  991. */
  992. int tls_fls_erase(u32 sector)
  993. {
  994. u32 addr;
  995. if (inside_fls == NULL)
  996. {
  997. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  998. return TLS_FLS_STATUS_EPERM;
  999. }
  1000. if (sector >= (inside_fls->density / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
  1001. {
  1002. TLS_DBGPRT_ERR("the sector to be erase overflow!\n");
  1003. return TLS_FLS_STATUS_EINVAL;
  1004. }
  1005. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1006. addr = sector * INSIDE_FLS_SECTOR_SIZE;
  1007. eraseSector(addr);
  1008. tls_os_sem_release(inside_fls->fls_lock);
  1009. return TLS_FLS_STATUS_OK;
  1010. }
  1011. static u8 *gsflscache = NULL;
  1012. //static u32 gsSecOffset = 0;
  1013. static u32 gsSector = 0;
  1014. /**
  1015. * @brief This function is used to flush the appoint sector
  1016. *
  1017. * @param None
  1018. *
  1019. * @return None
  1020. *
  1021. * @note None
  1022. */
  1023. static void tls_fls_flush_sector(void)
  1024. {
  1025. int i;
  1026. u32 addr;
  1027. if (gsSector < (inside_fls->density / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
  1028. {
  1029. addr = gsSector * INSIDE_FLS_SECTOR_SIZE;
  1030. eraseSector(addr);
  1031. for (i = 0; i < INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE; i++)
  1032. {
  1033. programPage(gsSector * INSIDE_FLS_SECTOR_SIZE +
  1034. i * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE,
  1035. &gsflscache[i * INSIDE_FLS_PAGE_SIZE]);
  1036. }
  1037. }
  1038. //gsSecOffset = 0;
  1039. }
  1040. /**
  1041. * @brief This function is used to fast write flash initialize
  1042. *
  1043. * @param None
  1044. *
  1045. * @retval TLS_FLS_STATUS_OK sucsess
  1046. * @retval other fail
  1047. *
  1048. * @note None
  1049. */
  1050. int tls_fls_fast_write_init(void)
  1051. {
  1052. if (inside_fls == NULL)
  1053. {
  1054. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1055. return TLS_FLS_STATUS_EPERM;
  1056. }
  1057. if (NULL != gsflscache)
  1058. {
  1059. TLS_DBGPRT_ERR("tls_fls_fast_write_init installed!\n");
  1060. return -1;
  1061. }
  1062. gsflscache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  1063. if (NULL == gsflscache)
  1064. {
  1065. TLS_DBGPRT_ERR("tls_fls_fast_write_init malloc err!\n");
  1066. return -1;
  1067. }
  1068. return TLS_FLS_STATUS_OK;
  1069. }
  1070. /**
  1071. * @brief This function is used to destroy fast write flash
  1072. *
  1073. * @param None
  1074. *
  1075. * @return None
  1076. *
  1077. * @note None
  1078. */
  1079. void tls_fls_fast_write_destroy(void)
  1080. {
  1081. if (NULL != gsflscache)
  1082. {
  1083. if (inside_fls == NULL)
  1084. {
  1085. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1086. return;
  1087. }
  1088. else
  1089. {
  1090. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1091. tls_fls_flush_sector();
  1092. tls_os_sem_release(inside_fls->fls_lock);
  1093. }
  1094. tls_mem_free(gsflscache);
  1095. gsflscache = NULL;
  1096. }
  1097. }
  1098. /**
  1099. * @brief This function is used to fast write data to the flash.
  1100. *
  1101. * @param[in] addr is byte offset addr for write to the flash
  1102. * @param[in] buf is the data buffer want to write to flash
  1103. * @param[in] length is the byte length want to write
  1104. *
  1105. * @retval TLS_FLS_STATUS_OK success
  1106. * @retval other fail
  1107. *
  1108. * @note None
  1109. */
  1110. int tls_fls_fast_write(u32 addr, u8 *buf, u32 length)
  1111. {
  1112. u32 sector, offset, maxlen, len;
  1113. if (inside_fls == NULL)
  1114. {
  1115. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1116. return TLS_FLS_STATUS_EPERM;
  1117. }
  1118. if(((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= inside_fls->density) || (length == 0) || (buf == NULL))
  1119. {
  1120. return TLS_FLS_STATUS_EINVAL;
  1121. }
  1122. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1123. sector = addr / INSIDE_FLS_SECTOR_SIZE;
  1124. offset = addr % INSIDE_FLS_SECTOR_SIZE;
  1125. maxlen = INSIDE_FLS_SECTOR_SIZE;
  1126. if ((sector != gsSector) && (gsSector != 0))
  1127. {
  1128. tls_fls_flush_sector();
  1129. }
  1130. gsSector = sector;
  1131. if (offset > 0)
  1132. {
  1133. maxlen -= offset;
  1134. }
  1135. while (length > 0)
  1136. {
  1137. len = (length > maxlen) ? maxlen : length;
  1138. MEMCPY(gsflscache + offset, buf, len);
  1139. if (offset + len >= INSIDE_FLS_SECTOR_SIZE)
  1140. {
  1141. tls_fls_flush_sector();
  1142. gsSector++;
  1143. }
  1144. offset = 0;
  1145. maxlen = INSIDE_FLS_SECTOR_SIZE;
  1146. sector++;
  1147. buf += len;
  1148. length -= len;
  1149. }
  1150. tls_os_sem_release(inside_fls->fls_lock);
  1151. return TLS_FLS_STATUS_OK;
  1152. }
  1153. /**
  1154. * @brief This function is used to erase flash all chip
  1155. *
  1156. * @param None
  1157. *
  1158. * @retval TLS_FLS_STATUS_OK sucsess
  1159. * @retval other fail
  1160. *
  1161. * @note None
  1162. */
  1163. int tls_fls_chip_erase(void)
  1164. {
  1165. int i, j;
  1166. u8 *cache;
  1167. if (inside_fls == NULL)
  1168. {
  1169. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1170. return TLS_FLS_STATUS_EPERM;
  1171. }
  1172. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1173. cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  1174. if (cache == NULL)
  1175. {
  1176. tls_os_sem_release(inside_fls->fls_lock);
  1177. TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  1178. return TLS_FLS_STATUS_ENOMEM;
  1179. }
  1180. for( i = 0; i < ( inside_fls->density - (INSIDE_FLS_SECBOOT_ADDR & 0xFFFFF)) / INSIDE_FLS_SECTOR_SIZE; i ++)
  1181. {
  1182. flashRead(INSIDE_FLS_SECBOOT_ADDR + i * INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE);
  1183. for (j = 0; j < INSIDE_FLS_SECTOR_SIZE; j++)
  1184. {
  1185. if (cache[j] != 0xFF)
  1186. {
  1187. eraseSector(INSIDE_FLS_SECBOOT_ADDR + i * INSIDE_FLS_SECTOR_SIZE);
  1188. break;
  1189. }
  1190. }
  1191. }
  1192. tls_mem_free(cache);
  1193. tls_os_sem_release(inside_fls->fls_lock);
  1194. return TLS_FLS_STATUS_OK;
  1195. }
  1196. /**
  1197. * @brief This function is used to get flash param
  1198. *
  1199. * @param[in] type the type of the param need to get
  1200. * @param[out] param point to addr of out param
  1201. *
  1202. * @retval TLS_FLS_STATUS_OK sucsess
  1203. * @retval other fail
  1204. *
  1205. * @note None
  1206. */
  1207. int tls_fls_get_param(u8 type, void *param)
  1208. {
  1209. int err;
  1210. if (inside_fls == NULL)
  1211. {
  1212. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1213. return TLS_FLS_STATUS_EPERM;
  1214. }
  1215. if (param == NULL)
  1216. {
  1217. return TLS_FLS_STATUS_EINVAL;
  1218. }
  1219. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1220. err = TLS_FLS_STATUS_OK;
  1221. switch (type)
  1222. {
  1223. case TLS_FLS_PARAM_TYPE_ID:
  1224. *((u32 *) param) = 0x2013;
  1225. break;
  1226. case TLS_FLS_PARAM_TYPE_SIZE:
  1227. *((u32 *) param) = inside_fls->density;
  1228. break;
  1229. case TLS_FLS_PARAM_TYPE_PAGE_SIZE:
  1230. *((u32 *) param) = INSIDE_FLS_PAGE_SIZE;
  1231. break;
  1232. case TLS_FLS_PARAM_TYPE_PROG_SIZE:
  1233. *((u32 *) param) = INSIDE_FLS_PAGE_SIZE;
  1234. break;
  1235. case TLS_FLS_PARAM_TYPE_SECTOR_SIZE:
  1236. *((u32 *) param) = INSIDE_FLS_SECTOR_SIZE;
  1237. break;
  1238. default:
  1239. TLS_DBGPRT_WARNING("invalid parameter ID!\n");
  1240. err = TLS_FLS_STATUS_EINVAL;
  1241. break;
  1242. }
  1243. tls_os_sem_release(inside_fls->fls_lock);
  1244. return err;
  1245. }
  1246. /**
  1247. * @brief This function is used to initialize the flash module
  1248. *
  1249. * @param None
  1250. *
  1251. * @retval TLS_FLS_STATUS_OK sucsess
  1252. * @retval other fail
  1253. *
  1254. * @note None
  1255. */
  1256. int tls_fls_init(void)
  1257. {
  1258. struct tls_inside_fls *fls;
  1259. int err;
  1260. if (inside_fls != NULL)
  1261. {
  1262. TLS_DBGPRT_ERR("flash driver module has been installed!\n");
  1263. return TLS_FLS_STATUS_EBUSY;
  1264. }
  1265. fls = (struct tls_inside_fls *) tls_mem_alloc(sizeof(struct tls_inside_fls));
  1266. if (fls == NULL)
  1267. {
  1268. TLS_DBGPRT_ERR("allocate @inside_fls fail!\n");
  1269. return TLS_FLS_STATUS_ENOMEM;
  1270. }
  1271. memset(fls, 0, sizeof(*fls));
  1272. err = tls_os_sem_create(&fls->fls_lock, 1);
  1273. if (err != TLS_OS_SUCCESS)
  1274. {
  1275. tls_mem_free(fls);
  1276. TLS_DBGPRT_ERR("create semaphore @fls_lock fail!\n");
  1277. return TLS_FLS_STATUS_ENOMEM;
  1278. }
  1279. fls->flashid = readRID();
  1280. //printf("flashid %x\n", fls->flashid);
  1281. fls->density = getFlashDensity();
  1282. fls->OTPWRParam.pageSize = 256;
  1283. switch(fls->flashid)
  1284. {
  1285. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  1286. if (fls->density == 0x100000)
  1287. {
  1288. fls->OTPWRParam.eraseSize = 1024;
  1289. }
  1290. else if (fls->density == 0x400000)
  1291. {
  1292. fls->OTPWRParam.eraseSize = 2048;
  1293. }
  1294. else
  1295. {
  1296. fls->OTPWRParam.eraseSize = 256;
  1297. }
  1298. break;
  1299. case SPIFLASH_MID_GD:
  1300. fls->OTPWRParam.eraseSize = 1024;
  1301. break;
  1302. case SPIFLASH_MID_FUDANMICRO:
  1303. fls->OTPWRParam.eraseSize = 1024;
  1304. if(fls->density <= (1 << 20))//8Mbit
  1305. {
  1306. fls->OTPWRParam.eraseSize = 256;
  1307. }
  1308. break;
  1309. case SPIFLASH_MID_TSINGTENG:
  1310. case SPIFLASH_MID_BOYA:
  1311. case SPIFLASH_MID_XMC:
  1312. case SPIFLASH_MID_WINBOND:
  1313. fls->OTPWRParam.eraseSize = 256;
  1314. break;
  1315. case SPIFLASH_MID_PUYA:
  1316. fls->OTPWRParam.eraseSize = 512;
  1317. break;
  1318. case SPIFLASH_MID_XTX:
  1319. case SPIFLASH_MID_ESMT:
  1320. fls->OTPWRParam.eraseSize = 0;//not support
  1321. break;
  1322. default:
  1323. tls_mem_free(fls);
  1324. TLS_DBGPRT_ERR("flash is not supported!\n");
  1325. return TLS_FLS_STATUS_ENOSUPPORT;
  1326. }
  1327. inside_fls = fls;
  1328. return TLS_FLS_STATUS_OK;
  1329. }
  1330. int tls_fls_exit(void)
  1331. {
  1332. TLS_DBGPRT_FLASH_INFO("Not support flash driver module uninstalled!\n");
  1333. return TLS_FLS_STATUS_EPERM;
  1334. }
  1335. /**
  1336. * @brief This function is used to initialize system parameter postion by flash density
  1337. *
  1338. * @param None
  1339. *
  1340. * @retval None
  1341. *
  1342. * @note must be called before function tls_param_init
  1343. */
  1344. void tls_fls_sys_param_postion_init(void)
  1345. {
  1346. unsigned int density = 0;
  1347. int err;
  1348. err = tls_fls_get_param(TLS_FLS_PARAM_TYPE_SIZE, (void *)&density);
  1349. if (TLS_FLS_STATUS_OK == err)
  1350. {
  1351. TLS_FLASH_END_ADDR = (FLASH_BASE_ADDR|density) - 1;
  1352. TLS_FLASH_OTA_FLAG_ADDR = (FLASH_BASE_ADDR|density) - 0x1000;
  1353. TLS_FLASH_PARAM_RESTORE_ADDR = (FLASH_BASE_ADDR|density) - 0x2000;
  1354. TLS_FLASH_PARAM2_ADDR = (FLASH_BASE_ADDR|density) - 0x3000;
  1355. TLS_FLASH_PARAM1_ADDR = (FLASH_BASE_ADDR|density) - 0x4000;
  1356. TLS_FLASH_PARAM_DEFAULT = (FLASH_BASE_ADDR|density) - 0x5000;
  1357. TLS_FLASH_MESH_PARAM_ADDR = (FLASH_BASE_ADDR|density) - 0x6000;
  1358. }
  1359. else
  1360. {
  1361. TLS_DBGPRT_ERR("system parameter postion use default!\n");
  1362. }
  1363. }