wm_internal_fls.c 38 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556
  1. /**
  2. * @file wm_internal_fls.c
  3. *
  4. * @brief flash Driver Module
  5. *
  6. * @author dave
  7. *
  8. * Copyright (c) 2015 Winner Microelectronics Co., Ltd.
  9. */
  10. #include <stdio.h>
  11. #include <string.h>
  12. #include <stdlib.h>
  13. #include "wm_dbg.h"
  14. #include "wm_mem.h"
  15. #include "list.h"
  16. #include "wm_regs.h"
  17. #include "wm_internal_flash.h"
  18. #include "wm_flash_map.h"
  19. static struct tls_inside_fls *inside_fls = NULL;
  20. // read/write use the same cache, protect by inside_fls->fls_lock
  21. static u8 tls_fls_cache[INSIDE_FLS_SECTOR_SIZE];
  22. /**System parameter, default for 2M flash*/
  23. unsigned int TLS_FLASH_MESH_PARAM_ADDR = (0x81FA000UL);
  24. unsigned int TLS_FLASH_PARAM_DEFAULT = (0x81FB000UL);
  25. unsigned int TLS_FLASH_PARAM1_ADDR = (0x81FC000UL);
  26. unsigned int TLS_FLASH_PARAM2_ADDR = (0x81FD000UL);
  27. unsigned int TLS_FLASH_PARAM_RESTORE_ADDR = (0x81FE000UL);
  28. unsigned int TLS_FLASH_OTA_FLAG_ADDR = (0x81FF000UL);
  29. unsigned int TLS_FLASH_END_ADDR = (0x81FFFFFUL);
  30. static vu32 read_first_value(void)
  31. {
  32. return M32(RSA_BASE_ADDRESS);
  33. }
  34. static void writeEnable(void)
  35. {
  36. M32(HR_FLASH_CMD_ADDR) = 0x6;
  37. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  38. }
  39. unsigned char readRID(void)
  40. {
  41. M32(HR_FLASH_CMD_ADDR) = 0x2c09F;
  42. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  43. return read_first_value() & 0xFF;
  44. }
  45. static void writeBpBit_for_1wreg(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  46. {
  47. int status = 0;
  48. int bpstatus = 0;
  49. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  50. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  51. status = read_first_value() & 0xFF;
  52. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  53. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  54. status |= (read_first_value() & 0xFF) << 8;
  55. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  56. if ((status & 0x407C) != (bpstatus|(cmp<<14)))
  57. {
  58. status = (status & 0xBF83) | bpstatus | (cmp << 14);
  59. /*Write Enable*/
  60. M32(HR_FLASH_CMD_ADDR) = 0x6;
  61. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  62. M32(RSA_BASE_ADDRESS) = status;
  63. M32(HR_FLASH_CMD_ADDR) = 0x1A001;
  64. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  65. }
  66. }
  67. static void writeBpBit_for_2wreg(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  68. {
  69. int status = 0;
  70. int bpstatus = 0;
  71. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  72. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  73. status = read_first_value() & 0xFF;
  74. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  75. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  76. status |= (read_first_value() & 0xFF) << 8;
  77. /*Write Enable*/
  78. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  79. if ((bpstatus != (status & 0x7C)))
  80. {
  81. bpstatus = (status & 0x83) | bpstatus;
  82. M32(HR_FLASH_CMD_ADDR) = 0x6;
  83. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  84. M32(RSA_BASE_ADDRESS) = bpstatus;
  85. M32(HR_FLASH_CMD_ADDR) = 0xA001;
  86. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  87. }
  88. if (((status & 0x4000)>>8) != (cmp << 6))
  89. {
  90. M32(HR_FLASH_CMD_ADDR) = 0x6;
  91. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  92. status = ((status>>8) & 0xBF) | (cmp << 6);
  93. M32(RSA_BASE_ADDRESS) = status;
  94. M32(HR_FLASH_CMD_ADDR) = 0xA031;
  95. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  96. }
  97. }
  98. static void writeESMTBpBit(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0)
  99. {
  100. int status = 0;
  101. int bpstatus = 0;
  102. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  103. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  104. status = read_first_value() & 0xFF;
  105. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  106. status = (status & 0x83) | bpstatus;
  107. /*Write Enable*/
  108. M32(HR_FLASH_CMD_ADDR) = 0x6;
  109. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  110. bpstatus = (bp4 << 6) | (bp3 << 5) | (bp2 << 4) | (bp1 << 3) | (bp0 << 2);
  111. status = (status & 0x83) | bpstatus | (cmp << 14);
  112. M32(RSA_BASE_ADDRESS) = status;
  113. M32(HR_FLASH_CMD_ADDR) = 0x0A001;
  114. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  115. M32(HR_FLASH_CMD_ADDR) = 0x0C085;
  116. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  117. status = read_first_value() & 0xFF;
  118. /*Write Enable*/
  119. M32(HR_FLASH_CMD_ADDR) = 0x6;
  120. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  121. status = (status & 0xBF) | (cmp << 6);
  122. M32(RSA_BASE_ADDRESS) = status;
  123. M32(HR_FLASH_CMD_ADDR) = 0x0A0C1;
  124. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  125. }
  126. static int flashunlock(void)
  127. {
  128. switch(readRID())
  129. {
  130. case SPIFLASH_MID_GD:
  131. case SPIFLASH_MID_TSINGTENG:
  132. writeBpBit_for_1wreg(0, 0, 0, 0, 0, 0);
  133. break;
  134. case SPIFLASH_MID_PUYA:
  135. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  136. if (inside_fls->density == 0x100000)/*PUYA 1M Flash use 1 register to set lock/unlock*/
  137. {
  138. writeBpBit_for_1wreg(0, 0, 0, 0, 0, 0);
  139. }
  140. else
  141. {
  142. writeBpBit_for_2wreg(0, 0, 0, 0, 0, 0);
  143. }
  144. break;
  145. case SPIFLASH_MID_XTX:
  146. case SPIFLASH_MID_BOYA:
  147. case SPIFLASH_MID_FUDANMICRO:
  148. case SPIFLASH_MID_XMC:
  149. writeBpBit_for_2wreg(0, 0, 0, 0, 0, 0);
  150. break;
  151. case SPIFLASH_MID_ESMT:
  152. writeESMTBpBit(0, 0, 0, 0, 0, 0);
  153. break;
  154. default:
  155. return -1;
  156. }
  157. return 0;
  158. }
  159. static int flashlock(void)
  160. {
  161. switch(readRID())
  162. {
  163. case SPIFLASH_MID_GD:
  164. case SPIFLASH_MID_TSINGTENG:
  165. writeBpBit_for_1wreg(0, 1, 1, 0, 1, 0);
  166. break;
  167. case SPIFLASH_MID_PUYA:
  168. case SPIFLASH_MID_TSINGTENG_1MB_4MB:
  169. if (inside_fls->density == 0x100000) /*PUYA 1M Flash use 1 register to set lock/unlock*/
  170. {
  171. writeBpBit_for_1wreg(0, 1, 1, 0, 1, 0);
  172. }
  173. else
  174. {
  175. writeBpBit_for_2wreg(0, 1, 1, 0, 1, 0);
  176. }
  177. break;
  178. case SPIFLASH_MID_XTX:
  179. case SPIFLASH_MID_BOYA:
  180. case SPIFLASH_MID_FUDANMICRO:
  181. case SPIFLASH_MID_XMC:
  182. writeBpBit_for_2wreg(0, 1, 1, 0, 1, 0);
  183. break;
  184. case SPIFLASH_MID_ESMT:
  185. writeESMTBpBit(0, 1, 1, 0, 1, 0);
  186. break;
  187. default:
  188. return -1;/*do not clear QIO Mode*/
  189. }
  190. return 0;
  191. }
  192. static void writeLbBit_for_1wreg(unsigned int val)
  193. {
  194. int status = 0;
  195. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  196. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  197. status = read_first_value() & 0xFF;
  198. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  199. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  200. status |= (read_first_value() & 0xFF) << 8;
  201. /*Write Enable*/
  202. M32(HR_FLASH_CMD_ADDR) = 0x6;
  203. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  204. status |= (val);
  205. M32(RSA_BASE_ADDRESS) = status;
  206. M32(HR_FLASH_CMD_ADDR) = 0x1A001;
  207. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  208. }
  209. static void writeLbBit_for_2wreg(unsigned int val)
  210. {
  211. int status = 0;
  212. M32(HR_FLASH_CMD_ADDR) = 0x0C005;
  213. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  214. status = read_first_value() & 0xFF;
  215. M32(HR_FLASH_CMD_ADDR) = 0x0C035;
  216. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  217. status |= (read_first_value() & 0xFF) << 8;
  218. /*Write Enable*/
  219. M32(HR_FLASH_CMD_ADDR) = 0x6;
  220. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  221. status |= (val);
  222. status = (status>>8);
  223. M32(RSA_BASE_ADDRESS) = status;
  224. M32(HR_FLASH_CMD_ADDR) = 0xA031;
  225. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  226. }
  227. static int programSR(unsigned int cmd, unsigned long addr, unsigned char *buf, unsigned int sz)
  228. {
  229. unsigned long base_addr = 0;
  230. unsigned int size = 0;
  231. if (sz > INSIDE_FLS_PAGE_SIZE)
  232. {
  233. sz = INSIDE_FLS_PAGE_SIZE;
  234. }
  235. base_addr = RSA_BASE_ADDRESS;
  236. size = sz;
  237. while(size)
  238. {
  239. M32(base_addr) = *((unsigned long *)buf);
  240. base_addr += 4;
  241. buf += 4;
  242. size -= 4;
  243. }
  244. writeEnable();
  245. M32(HR_FLASH_CMD_ADDR) = cmd | ((sz - 1) << 16);
  246. M32(HR_FLASH_ADDR) = (addr & 0x1FFFFFF);
  247. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  248. return 0;
  249. }
  250. static int programPage (unsigned long adr, unsigned long sz, unsigned char *buf)
  251. {
  252. programSR(0x80009002, adr, buf, sz);
  253. return(0);
  254. }
  255. static int eraseSR(unsigned int cmd, unsigned long addr)
  256. {
  257. /*Write Enable*/
  258. writeEnable();
  259. M32(HR_FLASH_CMD_ADDR) = cmd;
  260. M32(HR_FLASH_ADDR) = (addr & 0x1FFFFFF);
  261. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  262. return 0;
  263. }
  264. static int eraseSector (unsigned long adr)
  265. {
  266. eraseSR(0x80000820, adr);
  267. return (0); // Finished without Errors
  268. }
  269. #if 0
  270. /*only for XT806 c400 flash*/
  271. static int erasePage (unsigned long addr)
  272. {
  273. eraseSR(0x80000881, addr);
  274. return (0); // Finished without Errors
  275. }
  276. #endif
  277. static unsigned int getFlashDensity(void)
  278. {
  279. unsigned char density = 0;
  280. M32(HR_FLASH_CMD_ADDR) = 0x2c09F;
  281. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  282. density = ((read_first_value() & 0xFFFFFF) >> 16) & 0xFF;
  283. // printf("density %x\n", density);
  284. if (density && (density <= 0x21)) /*just limit to (1<<33UL) Byte*/
  285. {
  286. return (1 << density);
  287. }
  288. return 0;
  289. }
  290. /*sr start*/
  291. /************************************************************
  292. addr:
  293. For GD, address:0x000,0x100
  294. For ESMT, address:0xFF000,0xFF100
  295. For WINBOND, address:0x1000
  296. *************************************************************/
  297. int readSR(unsigned int cmd, unsigned long addr, unsigned char *buf, unsigned long sz)
  298. {
  299. int i = 0;
  300. int word = sz / 4;
  301. int byte = sz % 4;
  302. unsigned long addr_read;
  303. M32(HR_FLASH_CMD_ADDR) = cmd | (((sz - 1) & 0x3FF) << 16);
  304. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  305. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  306. addr_read = RSA_BASE_ADDRESS;
  307. for(i = 0; i < word; i ++)
  308. {
  309. M32(buf) = M32(addr_read);
  310. buf += 4;
  311. addr_read += 4;
  312. }
  313. if(byte > 0)
  314. {
  315. M32(buf) = M32(addr_read);
  316. buf += 3; //point last byte
  317. while(byte)
  318. {
  319. *buf = 0;
  320. buf --;
  321. byte --;
  322. }
  323. }
  324. return 0;
  325. }
  326. void flashSRRW(unsigned long offset, unsigned char *buf, unsigned long sz, unsigned char *backbuf, unsigned int backlen, unsigned int rd)
  327. {
  328. #define SR_TOTAL_SZ (512)
  329. #define SR_PROGRAM_SZE (256)
  330. unsigned int i;
  331. unsigned int j;
  332. unsigned int baseaddr = 0;
  333. unsigned int sectoroffset = 0;
  334. unsigned int sectorsize = 0;
  335. unsigned int sectornum = 0;
  336. unsigned int remainsz;
  337. unsigned int erasecmd = 0;
  338. unsigned int readcmd = 0;
  339. unsigned int writecmd = 0;
  340. unsigned char flashid = 0;
  341. if (!buf || ((rd == 0) && ( !backbuf || (backlen < 512))))
  342. {
  343. return;
  344. }
  345. flashid = readRID();
  346. switch(flashid)
  347. {
  348. case SPIFLASH_MID_GD:
  349. baseaddr = 0x0;
  350. sectoroffset = 256;
  351. sectorsize = 256;
  352. sectornum = 2;
  353. erasecmd = 0x80000844;
  354. readcmd = 0xBC00C048;
  355. writecmd = 0x80009042;
  356. break;
  357. case SPIFLASH_MID_ESMT:
  358. {
  359. baseaddr = 0xFF000;
  360. sectoroffset = 0;
  361. sectorsize = 512;
  362. sectornum = 1;
  363. erasecmd = 0x80000820;
  364. readcmd = 0xBC00C00B;
  365. writecmd = 0x80009002;
  366. M32(HR_FLASH_CMD_ADDR) = 0x3A; /*enter OTP*/
  367. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  368. }
  369. break;
  370. case SPIFLASH_MID_PUYA:
  371. baseaddr = 0x1000;
  372. sectoroffset = 0;
  373. sectorsize = 512;
  374. sectornum = 1;
  375. erasecmd = 0x80000844;
  376. readcmd = 0xBC00C048;
  377. writecmd = 0x80009042;
  378. break;
  379. default:
  380. {
  381. }
  382. break;
  383. }
  384. for (i = 0 ; i < sectornum; i++)
  385. {
  386. readSR(readcmd, baseaddr + sectoroffset * i, backbuf + i * sectorsize, sectorsize);
  387. }
  388. if (rd)
  389. {
  390. for(i = 0; i < sz; i++) //Copy
  391. {
  392. buf[i] = backbuf[i + offset];
  393. }
  394. }
  395. else
  396. {
  397. for (i = 0; i < sectornum ; i++)
  398. {
  399. eraseSR(erasecmd, baseaddr + sectoroffset * i);
  400. }
  401. remainsz = (sz < (SR_TOTAL_SZ - offset)) ? sz : (SR_TOTAL_SZ - offset);
  402. for(i = 0; i < remainsz; i++)
  403. {
  404. backbuf[i + offset] = buf[i];
  405. }
  406. for ( i = 0; i < sectornum; i++)
  407. {
  408. for (j = 0; j < (sectorsize / SR_PROGRAM_SZE); j++)
  409. {
  410. programSR(writecmd, baseaddr + sectoroffset * i + j * SR_PROGRAM_SZE, backbuf, SR_PROGRAM_SZE);
  411. backbuf += SR_PROGRAM_SZE;
  412. }
  413. }
  414. }
  415. if (SPIFLASH_MID_ESMT == flashid)
  416. {
  417. /*Write Disable*/
  418. M32(HR_FLASH_CMD_ADDR) = 0x4;
  419. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  420. }
  421. }
  422. /*sr end*/
  423. int __readByCMD(unsigned char cmd, unsigned long addr, unsigned char *buf, unsigned long sz)
  424. {
  425. int i = 0;
  426. int word = sz / 4;
  427. int byte = sz % 4;
  428. unsigned long addr_read;
  429. if (!(M32(HR_FLASH_CR)&0x1))/*non-QIO mode, only single line command can be used*/
  430. {
  431. if (cmd > 0x0B)
  432. {
  433. cmd = 0x0B;
  434. }
  435. }
  436. switch (cmd)
  437. {
  438. case 0x03:
  439. M32(HR_FLASH_CMD_ADDR) = 0x8000C003 | (((sz - 1) & 0x3FF) << 16);
  440. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  441. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  442. break;
  443. case 0x0B:
  444. if((M32(HR_FLASH_CR) & 0x2) == 0x2)
  445. {
  446. M32(HR_FLASH_CMD_ADDR) = 0xB400C00B | (((sz - 1) & 0x3FF) << 16);
  447. }
  448. else
  449. {
  450. M32(HR_FLASH_CMD_ADDR) = 0xBC00C00B | (((sz - 1) & 0x3FF) << 16);
  451. }
  452. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  453. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  454. break;
  455. case 0xBB:
  456. M32(HR_FLASH_CMD_ADDR) = 0xE400C0BB | (((sz - 1) & 0x3FF) << 16);
  457. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  458. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  459. break;
  460. case 0xEB:
  461. M32(HR_FLASH_CMD_ADDR) = 0xEC00C0EB | (((sz - 1) & 0x3FF) << 16);
  462. M32(HR_FLASH_ADDR) = addr & 0x1FFFFFF;
  463. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  464. break;
  465. default:
  466. return -1;
  467. }
  468. // printf("delay delay delay delay\n");
  469. // dumpUint32("readByCMD RSA_BASE_ADDRESS", RSA_BASE_ADDRESS, sz/4);
  470. addr_read = RSA_BASE_ADDRESS;
  471. for(i = 0; i < word; i ++)
  472. {
  473. M32(buf) = M32(addr_read);
  474. buf += 4;
  475. addr_read += 4;
  476. }
  477. if(byte > 0)
  478. {
  479. M32(buf) = M32(addr_read);
  480. buf += 3; //point last byte
  481. byte = 4 - byte;
  482. while(byte)
  483. {
  484. *buf = 0;
  485. buf --;
  486. byte --;
  487. }
  488. }
  489. return 0;
  490. }
  491. /**
  492. * @brief This function is used to read data from the flash.
  493. *
  494. * @param[in] cmd 0xEB in QSPI mode; 0x0b in SPI mode.
  495. * @param[in] addr is byte offset addr for read from the flash.
  496. * @param[in] buf is user for data buffer of flash read
  497. * @param[in] len is byte length for read.
  498. *
  499. * @retval TLS_FLS_STATUS_OK if read sucsess
  500. * @retval TLS_FLS_STATUS_EPERM if inside fls does not initialized.
  501. *
  502. * @note None
  503. */
  504. int readByCMD(unsigned char cmd, unsigned long addr, unsigned char *buf, unsigned long sz)
  505. {
  506. if (inside_fls == NULL)
  507. {
  508. return TLS_FLS_STATUS_EPERM;
  509. }
  510. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  511. __readByCMD(cmd, addr, buf, sz);
  512. tls_os_sem_release(inside_fls->fls_lock);
  513. return TLS_FLS_STATUS_OK;
  514. }
  515. int flashRead(unsigned long addr, unsigned char *buf, unsigned long sz)
  516. {
  517. #define INSIDE_FLS_MAX_RD_SIZE (1024)
  518. unsigned int flash_addr;
  519. unsigned int sz_pagenum = 0;
  520. unsigned int sz_remain = 0;
  521. int i = 0;
  522. int page_offset = addr & (INSIDE_FLS_PAGE_SIZE - 1);
  523. unsigned int max_size = 0;
  524. if ((page_offset == 0)
  525. && (((unsigned int)buf&0x3) == 0)
  526. && ((sz&0x3) == 0))/*Use 4-bytes aligned and buf must be 4 times, sz must be 4 times*/
  527. {
  528. flash_addr = addr;
  529. if (sz >= 512)
  530. {
  531. max_size = INSIDE_FLS_MAX_RD_SIZE;
  532. }
  533. else
  534. {
  535. max_size = INSIDE_FLS_PAGE_SIZE;
  536. }
  537. sz_pagenum = sz / max_size;
  538. sz_remain = sz % max_size;
  539. for (i = 0; i < sz_pagenum; i++)
  540. {
  541. __readByCMD(0xEB, flash_addr, (unsigned char *)buf, max_size);
  542. buf += max_size;
  543. flash_addr += max_size;
  544. }
  545. if (sz_remain)
  546. {
  547. __readByCMD(0xEB, flash_addr, (unsigned char *)buf, sz_remain);
  548. }
  549. }
  550. else
  551. {
  552. char *cache = tls_fls_cache;
  553. // cache = tls_mem_alloc(INSIDE_FLS_PAGE_SIZE);
  554. // if (cache == NULL)
  555. // {
  556. // TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  557. // return TLS_FLS_STATUS_ENOMEM;
  558. // }
  559. flash_addr = addr & ~(INSIDE_FLS_PAGE_SIZE - 1);
  560. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, INSIDE_FLS_PAGE_SIZE);
  561. if (sz > INSIDE_FLS_PAGE_SIZE - page_offset)
  562. {
  563. MEMCPY(buf, cache + page_offset, INSIDE_FLS_PAGE_SIZE - page_offset);
  564. buf += INSIDE_FLS_PAGE_SIZE - page_offset;
  565. flash_addr += INSIDE_FLS_PAGE_SIZE;
  566. sz_pagenum = (sz - (INSIDE_FLS_PAGE_SIZE - page_offset)) / INSIDE_FLS_PAGE_SIZE;
  567. sz_remain = (sz - (INSIDE_FLS_PAGE_SIZE - page_offset)) % INSIDE_FLS_PAGE_SIZE;
  568. for (i = 0; i < sz_pagenum; i++)
  569. {
  570. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, INSIDE_FLS_PAGE_SIZE);
  571. MEMCPY(buf, cache, INSIDE_FLS_PAGE_SIZE);
  572. buf += INSIDE_FLS_PAGE_SIZE;
  573. flash_addr += INSIDE_FLS_PAGE_SIZE;
  574. }
  575. if (sz_remain)
  576. {
  577. __readByCMD(0xEB, flash_addr, (unsigned char *)cache, sz_remain + (4- sz_remain%4));
  578. MEMCPY(buf, cache, sz_remain);
  579. }
  580. }
  581. else
  582. {
  583. MEMCPY(buf, cache + page_offset, sz);
  584. }
  585. // tls_mem_free(cache);
  586. }
  587. return 0;
  588. }
  589. /**
  590. * @brief This function is used to unlock flash protect area [0x0~0x2000].
  591. *
  592. * @param None
  593. *
  594. * @return None
  595. *
  596. * @note None
  597. */
  598. int tls_flash_unlock(void)
  599. {
  600. // return flashunlock();
  601. return 0;
  602. }
  603. /**
  604. * @brief This function is used to lock flash protect area [0x0~0x2000].
  605. *
  606. * @param None
  607. *
  608. * @return None
  609. *
  610. * @note None
  611. */
  612. int tls_flash_lock(void)
  613. {
  614. // return flashlock();
  615. return 0;
  616. }
  617. /**
  618. * @brief This function is used to semaphore protect.
  619. *
  620. * @param None
  621. *
  622. * @return None
  623. *
  624. * @note None
  625. */
  626. void tls_fls_sem_lock(void)
  627. {
  628. if (inside_fls == NULL)
  629. {
  630. return;
  631. }
  632. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  633. }
  634. /**
  635. * @brief This function is used to semaphore protect cancel.
  636. *
  637. * @param None
  638. *
  639. * @return None
  640. *
  641. * @note None
  642. */
  643. void tls_fls_sem_unlock(void)
  644. {
  645. if (inside_fls == NULL)
  646. {
  647. return;
  648. }
  649. tls_os_sem_release(inside_fls->fls_lock);
  650. }
  651. /**
  652. * @brief This function is used to read the unique id of the internal flash.
  653. *
  654. * @param[out] uuid Specified the address to save the uuid, the length must be greater than or equals to 18 bytes.
  655. *
  656. * @retval TLS_FLS_STATUS_OK if read sucsess
  657. * @retval TLS_FLS_STATUS_EIO if read fail
  658. *
  659. * @note The uuid's length must be greater than or equals to 18 bytes.
  660. */
  661. int tls_fls_read_unique_id(unsigned char *uuid)
  662. {
  663. unsigned int value = 0;
  664. unsigned int addr_read = 0;
  665. int i = 0;
  666. int len;
  667. unsigned char FLASH_BUF[20];
  668. unsigned char *addr = &FLASH_BUF[0];
  669. int dumy_bytes = 0;
  670. int uni_bytes = 0;
  671. unsigned char rid;
  672. int word;
  673. int byte;
  674. memset(uuid, 0xFF, 18);
  675. rid = readRID();
  676. switch(rid)
  677. {
  678. case SPIFLASH_MID_GD:
  679. case SPIFLASH_MID_PUYA:
  680. case SPIFLASH_MID_TSINGTENG:
  681. dumy_bytes = 4;
  682. uni_bytes = 16;
  683. break;
  684. case SPIFLASH_MID_WINBOND:
  685. case SPIFLASH_MID_FUDANMICRO:
  686. case SPIFLASH_MID_BOYA:
  687. case SPIFLASH_MID_XMC:
  688. dumy_bytes = 4;
  689. uni_bytes = 8;
  690. break;
  691. case SPIFLASH_MID_ESMT:
  692. case SPIFLASH_MID_XTX:
  693. default:
  694. return -1;
  695. }
  696. uuid[0] = rid;
  697. uuid[1] = (unsigned char)(uni_bytes & 0xFF);
  698. len = dumy_bytes + uni_bytes;
  699. word = len/4;
  700. byte = len%4;
  701. value = 0xC04B|((len-1) << 16);
  702. M32(HR_FLASH_CMD_ADDR) = value;
  703. M32(HR_FLASH_CMD_START) = CMD_START_Msk;
  704. addr_read = RSA_BASE_ADDRESS;
  705. for(i = 0;i < word; i ++)
  706. {
  707. M32(addr) = M32(addr_read);
  708. addr += 4;
  709. addr_read += 4;
  710. }
  711. if(byte > 0)
  712. {
  713. M32(addr) = M32(addr_read);
  714. addr += 3; //point last byte
  715. while(byte)
  716. {
  717. *addr = 0;
  718. addr --;
  719. byte --;
  720. }
  721. }
  722. addr = &FLASH_BUF[0];
  723. memcpy(&uuid[2], addr + dumy_bytes, uni_bytes);
  724. return 0;
  725. }
  726. int tls_fls_otp_read(u32 addr, u8 *buf, u32 len)
  727. {
  728. int err;
  729. int i = 0;
  730. int word = len/4;
  731. int byte = len%4;
  732. unsigned long addr_read = 0xBC00C048;
  733. volatile unsigned long value;
  734. unsigned long addr_offset = 0;
  735. unsigned long sz_need = len;
  736. if (inside_fls == NULL)
  737. {
  738. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  739. return TLS_FLS_STATUS_EPERM;
  740. }
  741. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  742. if(buf)
  743. {
  744. addr_offset = addr % 16;
  745. sz_need = (addr_offset + len + 16) / 16 * 16;
  746. addr = addr / 16 * 16;
  747. }
  748. M32(HR_FLASH_CMD_ADDR) = addr_read|(((sz_need-1)&0x3FF)<<16);
  749. M32(HR_FLASH_ADDR) = (addr&0x1FFFFFF);
  750. M32(HR_FLASH_CMD_START) = tls_reg_read32(HR_FLASH_CMD_START) | CMD_START_Msk;
  751. if(buf)
  752. {
  753. addr_read = RSA_BASE_ADDRESS + (addr_offset / 4 * 4);
  754. i = (4 - addr_offset % 4) % 4;
  755. if(i > len)
  756. {
  757. byte = len;
  758. }
  759. else
  760. {
  761. byte = i;
  762. }
  763. if(byte)
  764. {
  765. value = M32(addr_read);
  766. memcpy(buf, ((char *)&value) + 4 - i, byte);
  767. addr_read += 4;
  768. buf += byte;
  769. }
  770. word = (len - byte) / 4;
  771. for(i = 0;i < word; i ++)
  772. {
  773. value = M32(addr_read);
  774. memcpy(buf, (char*)&value, 4);
  775. buf += 4;
  776. addr_read += 4;
  777. }
  778. byte = (len - byte) % 4;
  779. if(byte > 0)
  780. {
  781. value = M32(addr_read);
  782. memcpy(buf, (char *)&value, byte);
  783. }
  784. }
  785. err = TLS_FLS_STATUS_OK;
  786. tls_os_sem_release(inside_fls->fls_lock);
  787. return err;
  788. }
  789. int tls_fls_otp_write(u32 addr, u8 *buf, u32 len)
  790. {
  791. int ret = 0;
  792. unsigned int erasecmd = 0x80000844;
  793. unsigned int writecmd = 0x80009042;
  794. uint32_t eraseAddr = 0;
  795. uint16_t eraseSize = 0;
  796. uint16_t pageSize = 0;
  797. unsigned char flashid = 0;
  798. int l = 0;
  799. unsigned char *backbuf = NULL;
  800. unsigned long size = 0;
  801. unsigned long p = 0;
  802. unsigned char *q = NULL;
  803. if (!buf)
  804. {
  805. return TLS_FLS_STATUS_EINVAL;
  806. }
  807. if (inside_fls == NULL)
  808. {
  809. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  810. return TLS_FLS_STATUS_EPERM;
  811. }
  812. eraseSize = inside_fls->OTPWRParam.eraseSize;
  813. pageSize = inside_fls->OTPWRParam.pageSize;
  814. if (eraseSize == 0 || pageSize == 0)
  815. {
  816. TLS_DBGPRT_ERR("flash type is not supported!\n");
  817. return TLS_FLS_STATUS_ENOSUPPORT;
  818. }
  819. eraseAddr = addr & ~(eraseSize - 1);
  820. if(addr < eraseAddr || len > eraseSize - (addr - eraseAddr))
  821. {
  822. return TLS_FLS_STATUS_EINVAL;
  823. }
  824. TLS_DBGPRT_INFO("addr 0x%x, eraseAddr 0x%x, eraseSize 0x%x, pageSize 0x%x\n", addr, eraseAddr, eraseSize, pageSize);
  825. backbuf = tls_mem_alloc(eraseSize);
  826. if (!backbuf)
  827. {
  828. ret = TLS_FLS_STATUS_ENOMEM;
  829. goto out;
  830. }
  831. p = eraseAddr;
  832. q = backbuf;
  833. size = eraseSize;
  834. while(size > 0)
  835. {
  836. l = size > pageSize ? pageSize : size;
  837. if(tls_fls_otp_read(p, q, l) != TLS_FLS_STATUS_OK)
  838. {
  839. ret = TLS_FLS_STATUS_EPERM;
  840. goto out;
  841. }
  842. q += l;
  843. p += l;
  844. size -= l;
  845. }
  846. eraseSR(erasecmd, eraseAddr);
  847. memcpy(backbuf + (addr - eraseAddr), buf, len);
  848. p = eraseAddr;
  849. q = backbuf;
  850. size = eraseSize;
  851. while(size > 0)
  852. {
  853. l = size > pageSize ? pageSize : size;
  854. programSR(writecmd, p, q, l);
  855. q += l;
  856. p += l;
  857. size -= l;
  858. }
  859. out:
  860. if(backbuf)
  861. tls_mem_free(backbuf);
  862. return ret;
  863. }
  864. int tls_fls_otp_lock(void)
  865. {
  866. if (inside_fls == NULL)
  867. {
  868. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  869. return TLS_FLS_STATUS_EPERM;
  870. }
  871. switch(inside_fls->flashid)
  872. {
  873. case SPIFLASH_MID_GD:
  874. case SPIFLASH_MID_TSINGTENG:
  875. writeLbBit_for_1wreg((1<<10));
  876. break;
  877. case SPIFLASH_MID_FUDANMICRO:
  878. writeLbBit_for_2wreg((1<<10));
  879. break;
  880. case SPIFLASH_MID_BOYA:
  881. case SPIFLASH_MID_XMC:
  882. case SPIFLASH_MID_WINBOND:
  883. case SPIFLASH_MID_PUYA:
  884. writeLbBit_for_2wreg((7<<11));
  885. break;
  886. case SPIFLASH_MID_XTX:
  887. case SPIFLASH_MID_ESMT:
  888. default:
  889. TLS_DBGPRT_ERR("flash is not supported!\n");
  890. return TLS_FLS_STATUS_ENOSUPPORT;
  891. }
  892. return 0;
  893. }
  894. /**
  895. * @brief This function is used to read data from the flash.
  896. *
  897. * @param[in] addr is byte offset addr for read from the flash.
  898. * @param[in] buf is user for data buffer of flash read
  899. * @param[in] len is byte length for read.
  900. *
  901. * @retval TLS_FLS_STATUS_OK if read sucsess
  902. * @retval TLS_FLS_STATUS_EIO if read fail
  903. *
  904. * @note None
  905. */
  906. int tls_fls_read(u32 addr, u8 *buf, u32 len)
  907. {
  908. int err;
  909. if (inside_fls == NULL)
  910. {
  911. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  912. return TLS_FLS_STATUS_EPERM;
  913. }
  914. if (((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= getFlashDensity()) || (len == 0) || (buf == NULL))
  915. {
  916. return TLS_FLS_STATUS_EINVAL;
  917. }
  918. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  919. flashRead(addr, buf, len);
  920. err = TLS_FLS_STATUS_OK;
  921. tls_os_sem_release(inside_fls->fls_lock);
  922. return err;
  923. }
  924. /**
  925. * @brief This function is used to write data to the flash.
  926. *
  927. * @param[in] addr is byte offset addr for write to the flash
  928. * @param[in] buf is the data buffer want to write to flash
  929. * @param[in] len is the byte length want to write
  930. *
  931. * @retval TLS_FLS_STATUS_OK if write flash success
  932. * @retval TLS_FLS_STATUS_EPERM if flash struct point is null
  933. * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed
  934. * @retval TLS_FLS_STATUS_EINVAL if argument is invalid
  935. * @retval TLS_FLS_STATUS_EIO if io error
  936. *
  937. * @note None
  938. */
  939. int tls_fls_write(u32 addr, u8 *buf, u32 len)
  940. {
  941. u8 *cache = tls_fls_cache;
  942. unsigned int secpos;
  943. unsigned int secoff;
  944. unsigned int secremain;
  945. unsigned int i;
  946. unsigned int offaddr;
  947. if (inside_fls == NULL)
  948. {
  949. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  950. return TLS_FLS_STATUS_EPERM;
  951. }
  952. if (((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= getFlashDensity()) || (len == 0) || (buf == NULL))
  953. {
  954. return TLS_FLS_STATUS_EINVAL;
  955. }
  956. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  957. // cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  958. // if (cache == NULL)
  959. // {
  960. // tls_os_sem_release(inside_fls->fls_lock);
  961. // TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  962. // return TLS_FLS_STATUS_ENOMEM;
  963. // }
  964. offaddr = addr & (INSIDE_FLS_BASE_ADDR - 1); //Offset of 0X08000000
  965. secpos = offaddr / INSIDE_FLS_SECTOR_SIZE; //Section addr
  966. secoff = (offaddr % INSIDE_FLS_SECTOR_SIZE); //Offset in section
  967. secremain = INSIDE_FLS_SECTOR_SIZE - secoff; // 扇区剩余空间大小
  968. if(len <= secremain)
  969. {
  970. secremain = len; //Not bigger with remain size in section
  971. }
  972. while (1)
  973. {
  974. flashRead(secpos * INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE);
  975. eraseSector(secpos * INSIDE_FLS_SECTOR_SIZE);
  976. for (i = 0; i < secremain; i++) // 复制
  977. {
  978. cache[i + secoff] = buf[i];
  979. }
  980. for (i = 0; i < (INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE); i++)
  981. {
  982. programPage(secpos * INSIDE_FLS_SECTOR_SIZE + i * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE, &cache[i * INSIDE_FLS_PAGE_SIZE]); //Write
  983. }
  984. if(len == secremain)
  985. {
  986. break; // 写入结束了
  987. }
  988. else // 写入未结束
  989. {
  990. secpos++; // 扇区地址增1
  991. secoff = 0; // 偏移位置为0
  992. buf += secremain; // 指针偏移
  993. len -= secremain;
  994. if(len > (INSIDE_FLS_SECTOR_SIZE))
  995. secremain = INSIDE_FLS_SECTOR_SIZE; // 下一个扇区还是写不完
  996. else
  997. secremain = len; //Next section will finish
  998. }
  999. }
  1000. // tls_mem_free(cache);
  1001. tls_os_sem_release(inside_fls->fls_lock);
  1002. return TLS_FLS_STATUS_OK;
  1003. }
  1004. /**
  1005. * @brief This function is used to erase the appoint sector
  1006. *
  1007. * @param[in] sector sector num of the flash, 4K byte a sector
  1008. *
  1009. * @retval TLS_FLS_STATUS_OK if read sucsess
  1010. * @retval other if read fail
  1011. *
  1012. * @note None
  1013. */
  1014. int tls_fls_erase(u32 sector)
  1015. {
  1016. u32 addr;
  1017. if (inside_fls == NULL)
  1018. {
  1019. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1020. return TLS_FLS_STATUS_EPERM;
  1021. }
  1022. if (sector >= (getFlashDensity() / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
  1023. {
  1024. TLS_DBGPRT_ERR("the sector to be erase overflow!\n");
  1025. return TLS_FLS_STATUS_EINVAL;
  1026. }
  1027. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1028. addr = sector * INSIDE_FLS_SECTOR_SIZE;
  1029. eraseSector(addr);
  1030. tls_os_sem_release(inside_fls->fls_lock);
  1031. return TLS_FLS_STATUS_OK;
  1032. }
  1033. static u8 *gsflscache = NULL;
  1034. //static u32 gsSecOffset = 0;
  1035. static u32 gsSector = 0;
  1036. /**
  1037. * @brief This function is used to flush the appoint sector
  1038. *
  1039. * @param None
  1040. *
  1041. * @return None
  1042. *
  1043. * @note None
  1044. */
  1045. static void tls_fls_flush_sector(void)
  1046. {
  1047. int i;
  1048. u32 addr;
  1049. if (gsSector < (getFlashDensity() / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
  1050. {
  1051. addr = gsSector * INSIDE_FLS_SECTOR_SIZE;
  1052. eraseSector(addr);
  1053. for (i = 0; i < INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE; i++)
  1054. {
  1055. programPage(gsSector * INSIDE_FLS_SECTOR_SIZE +
  1056. i * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE,
  1057. &gsflscache[i * INSIDE_FLS_PAGE_SIZE]);
  1058. }
  1059. }
  1060. //gsSecOffset = 0;
  1061. }
  1062. /**
  1063. * @brief This function is used to fast write flash initialize
  1064. *
  1065. * @param None
  1066. *
  1067. * @retval TLS_FLS_STATUS_OK sucsess
  1068. * @retval other fail
  1069. *
  1070. * @note None
  1071. */
  1072. int tls_fls_fast_write_init(void)
  1073. {
  1074. if (inside_fls == NULL)
  1075. {
  1076. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1077. return TLS_FLS_STATUS_EPERM;
  1078. }
  1079. if (NULL != gsflscache)
  1080. {
  1081. TLS_DBGPRT_ERR("tls_fls_fast_write_init installed!\n");
  1082. return -1;
  1083. }
  1084. gsflscache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  1085. if (NULL == gsflscache)
  1086. {
  1087. TLS_DBGPRT_ERR("tls_fls_fast_write_init malloc err!\n");
  1088. return -1;
  1089. }
  1090. return TLS_FLS_STATUS_OK;
  1091. }
  1092. /**
  1093. * @brief This function is used to destroy fast write flash
  1094. *
  1095. * @param None
  1096. *
  1097. * @return None
  1098. *
  1099. * @note None
  1100. */
  1101. void tls_fls_fast_write_destroy(void)
  1102. {
  1103. if (NULL != gsflscache)
  1104. {
  1105. if (inside_fls == NULL)
  1106. {
  1107. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1108. return;
  1109. }
  1110. else
  1111. {
  1112. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1113. tls_fls_flush_sector();
  1114. tls_os_sem_release(inside_fls->fls_lock);
  1115. }
  1116. tls_mem_free(gsflscache);
  1117. gsflscache = NULL;
  1118. }
  1119. }
  1120. /**
  1121. * @brief This function is used to fast write data to the flash.
  1122. *
  1123. * @param[in] addr is byte offset addr for write to the flash
  1124. * @param[in] buf is the data buffer want to write to flash
  1125. * @param[in] length is the byte length want to write
  1126. *
  1127. * @retval TLS_FLS_STATUS_OK success
  1128. * @retval other fail
  1129. *
  1130. * @note None
  1131. */
  1132. int tls_fls_fast_write(u32 addr, u8 *buf, u32 length)
  1133. {
  1134. u32 sector, offset, maxlen, len;
  1135. if (inside_fls == NULL)
  1136. {
  1137. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1138. return TLS_FLS_STATUS_EPERM;
  1139. }
  1140. if(((addr & (INSIDE_FLS_BASE_ADDR - 1)) >= getFlashDensity()) || (length == 0) || (buf == NULL))
  1141. {
  1142. return TLS_FLS_STATUS_EINVAL;
  1143. }
  1144. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1145. sector = addr / INSIDE_FLS_SECTOR_SIZE;
  1146. offset = addr % INSIDE_FLS_SECTOR_SIZE;
  1147. maxlen = INSIDE_FLS_SECTOR_SIZE;
  1148. if ((sector != gsSector) && (gsSector != 0))
  1149. {
  1150. tls_fls_flush_sector();
  1151. }
  1152. gsSector = sector;
  1153. if (offset > 0)
  1154. {
  1155. maxlen -= offset;
  1156. }
  1157. while (length > 0)
  1158. {
  1159. len = (length > maxlen) ? maxlen : length;
  1160. MEMCPY(gsflscache + offset, buf, len);
  1161. if (offset + len >= INSIDE_FLS_SECTOR_SIZE)
  1162. {
  1163. tls_fls_flush_sector();
  1164. gsSector++;
  1165. }
  1166. offset = 0;
  1167. maxlen = INSIDE_FLS_SECTOR_SIZE;
  1168. sector++;
  1169. buf += len;
  1170. length -= len;
  1171. }
  1172. tls_os_sem_release(inside_fls->fls_lock);
  1173. return TLS_FLS_STATUS_OK;
  1174. }
  1175. /**
  1176. * @brief This function is used to erase flash all chip
  1177. *
  1178. * @param None
  1179. *
  1180. * @retval TLS_FLS_STATUS_OK sucsess
  1181. * @retval other fail
  1182. *
  1183. * @note None
  1184. */
  1185. int tls_fls_chip_erase(void)
  1186. {
  1187. int i, j;
  1188. u8 *cache;
  1189. if (inside_fls == NULL)
  1190. {
  1191. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1192. return TLS_FLS_STATUS_EPERM;
  1193. }
  1194. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1195. cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE);
  1196. if (cache == NULL)
  1197. {
  1198. tls_os_sem_release(inside_fls->fls_lock);
  1199. TLS_DBGPRT_ERR("allocate sector cache memory fail!\n");
  1200. return TLS_FLS_STATUS_ENOMEM;
  1201. }
  1202. for( i = 0; i < ( getFlashDensity() - (INSIDE_FLS_SECBOOT_ADDR & 0xFFFFF)) / INSIDE_FLS_SECTOR_SIZE; i ++)
  1203. {
  1204. flashRead(INSIDE_FLS_SECBOOT_ADDR + i * INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE);
  1205. for (j = 0; j < INSIDE_FLS_SECTOR_SIZE; j++)
  1206. {
  1207. if (cache[j] != 0xFF)
  1208. {
  1209. eraseSector(INSIDE_FLS_SECBOOT_ADDR + i * INSIDE_FLS_SECTOR_SIZE);
  1210. break;
  1211. }
  1212. }
  1213. }
  1214. tls_mem_free(cache);
  1215. tls_os_sem_release(inside_fls->fls_lock);
  1216. return TLS_FLS_STATUS_OK;
  1217. }
  1218. /**
  1219. * @brief This function is used to get flash param
  1220. *
  1221. * @param[in] type the type of the param need to get
  1222. * @param[out] param point to addr of out param
  1223. *
  1224. * @retval TLS_FLS_STATUS_OK sucsess
  1225. * @retval other fail
  1226. *
  1227. * @note None
  1228. */
  1229. int tls_fls_get_param(u8 type, void *param)
  1230. {
  1231. int err;
  1232. if (inside_fls == NULL)
  1233. {
  1234. TLS_DBGPRT_ERR("flash driver module not beed installed!\n");
  1235. return TLS_FLS_STATUS_EPERM;
  1236. }
  1237. if (param == NULL)
  1238. {
  1239. return TLS_FLS_STATUS_EINVAL;
  1240. }
  1241. tls_os_sem_acquire(inside_fls->fls_lock, 0);
  1242. err = TLS_FLS_STATUS_OK;
  1243. switch (type)
  1244. {
  1245. case TLS_FLS_PARAM_TYPE_ID:
  1246. *((u32 *) param) = 0x2013;
  1247. break;
  1248. case TLS_FLS_PARAM_TYPE_SIZE:
  1249. *((u32 *) param) = getFlashDensity();
  1250. break;
  1251. case TLS_FLS_PARAM_TYPE_PAGE_SIZE:
  1252. *((u32 *) param) = INSIDE_FLS_PAGE_SIZE;
  1253. break;
  1254. case TLS_FLS_PARAM_TYPE_PROG_SIZE:
  1255. *((u32 *) param) = INSIDE_FLS_PAGE_SIZE;
  1256. break;
  1257. case TLS_FLS_PARAM_TYPE_SECTOR_SIZE:
  1258. *((u32 *) param) = INSIDE_FLS_SECTOR_SIZE;
  1259. break;
  1260. default:
  1261. TLS_DBGPRT_WARNING("invalid parameter ID!\n");
  1262. err = TLS_FLS_STATUS_EINVAL;
  1263. break;
  1264. }
  1265. tls_os_sem_release(inside_fls->fls_lock);
  1266. return err;
  1267. }
  1268. /**
  1269. * @brief This function is used to initialize the flash module
  1270. *
  1271. * @param None
  1272. *
  1273. * @retval TLS_FLS_STATUS_OK sucsess
  1274. * @retval other fail
  1275. *
  1276. * @note None
  1277. */
  1278. int tls_fls_init(void)
  1279. {
  1280. struct tls_inside_fls *fls;
  1281. int err;
  1282. if (inside_fls != NULL)
  1283. {
  1284. TLS_DBGPRT_ERR("flash driver module has been installed!\n");
  1285. return TLS_FLS_STATUS_EBUSY;
  1286. }
  1287. fls = (struct tls_inside_fls *) tls_mem_alloc(sizeof(struct tls_inside_fls));
  1288. if (fls == NULL)
  1289. {
  1290. TLS_DBGPRT_ERR("allocate @inside_fls fail!\n");
  1291. return TLS_FLS_STATUS_ENOMEM;
  1292. }
  1293. memset(fls, 0, sizeof(*fls));
  1294. err = tls_os_sem_create(&fls->fls_lock, 1);
  1295. if (err != TLS_OS_SUCCESS)
  1296. {
  1297. tls_mem_free(fls);
  1298. TLS_DBGPRT_ERR("create semaphore @fls_lock fail!\n");
  1299. return TLS_FLS_STATUS_ENOMEM;
  1300. }
  1301. fls->flashid = readRID();
  1302. // printf("flashid %x\n", fls->flashid);
  1303. fls->density = getFlashDensity();
  1304. fls->OTPWRParam.pageSize = 256;
  1305. switch(fls->flashid)
  1306. {
  1307. case SPIFLASH_MID_GD:
  1308. fls->OTPWRParam.eraseSize = 1024;
  1309. break;
  1310. case SPIFLASH_MID_FUDANMICRO:
  1311. fls->OTPWRParam.eraseSize = 1024;
  1312. if(fls->density <= (1 << 20))//8Mbit
  1313. {
  1314. fls->OTPWRParam.eraseSize = 256;
  1315. }
  1316. break;
  1317. case SPIFLASH_MID_TSINGTENG:
  1318. case SPIFLASH_MID_BOYA:
  1319. case SPIFLASH_MID_XMC:
  1320. case SPIFLASH_MID_WINBOND:
  1321. fls->OTPWRParam.eraseSize = 256;
  1322. break;
  1323. case SPIFLASH_MID_PUYA:
  1324. fls->OTPWRParam.eraseSize = 512;
  1325. break;
  1326. case SPIFLASH_MID_XTX:
  1327. case SPIFLASH_MID_ESMT:
  1328. fls->OTPWRParam.eraseSize = 0;//not support
  1329. break;
  1330. default:
  1331. tls_mem_free(fls);
  1332. TLS_DBGPRT_ERR("flash is not supported!\n");
  1333. return TLS_FLS_STATUS_ENOSUPPORT;
  1334. }
  1335. inside_fls = fls;
  1336. return TLS_FLS_STATUS_OK;
  1337. }
  1338. int tls_fls_exit(void)
  1339. {
  1340. TLS_DBGPRT_FLASH_INFO("Not support flash driver module uninstalled!\n");
  1341. return TLS_FLS_STATUS_EPERM;
  1342. }
  1343. /**
  1344. * @brief This function is used to initialize system parameter postion by flash density
  1345. *
  1346. * @param None
  1347. *
  1348. * @retval None
  1349. *
  1350. * @note must be called before function tls_param_init
  1351. */
  1352. void tls_fls_sys_param_postion_init(void)
  1353. {
  1354. unsigned int density = 0;
  1355. int err;
  1356. err = tls_fls_get_param(TLS_FLS_PARAM_TYPE_SIZE, (void *)&density);
  1357. if (TLS_FLS_STATUS_OK == err)
  1358. {
  1359. TLS_FLASH_END_ADDR = (FLASH_BASE_ADDR|density) - 1;
  1360. TLS_FLASH_OTA_FLAG_ADDR = (FLASH_BASE_ADDR|density) - 0x1000;
  1361. TLS_FLASH_PARAM_RESTORE_ADDR = (FLASH_BASE_ADDR|density) - 0x2000;
  1362. TLS_FLASH_PARAM2_ADDR = (FLASH_BASE_ADDR|density) - 0x3000;
  1363. TLS_FLASH_PARAM1_ADDR = (FLASH_BASE_ADDR|density) - 0x4000;
  1364. TLS_FLASH_PARAM_DEFAULT = (FLASH_BASE_ADDR|density) - 0x5000;
  1365. }
  1366. else
  1367. {
  1368. TLS_DBGPRT_ERR("system parameter postion use default!\n");
  1369. }
  1370. }