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@@ -0,0 +1,566 @@
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+/*
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+ * FreeRTOS Kernel V10.4.3
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+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
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+ * this software and associated documentation files (the "Software"), to deal in
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+ * the Software without restriction, including without limitation the rights to
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+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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+ * the Software, and to permit persons to whom the Software is furnished to do so,
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+ * subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in all
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+ * copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * https://www.FreeRTOS.org
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+ * https://github.com/FreeRTOS
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+ *
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+ */
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+
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+/*-----------------------------------------------------------
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+* Implementation of functions defined in portable.h for the ARM CM0 port.
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+*----------------------------------------------------------*/
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+
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+/* Scheduler includes. */
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+#include "FreeRTOS.h"
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+#include "task.h"
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+
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+/* Constants required to manipulate the NVIC. */
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+#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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+#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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+#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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+#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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+#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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+#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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+
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+/* Constants required to set up the initial stack. */
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+#define portINITIAL_XPSR ( 0x01000000 )
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+
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+/* The systick is a 24-bit counter. */
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+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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+
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+/* A fiddle factor to estimate the number of SysTick counts that would have
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+ * occurred while the SysTick counter is stopped during tickless idle
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+ * calculations. */
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+#ifndef portMISSED_COUNTS_FACTOR
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+ #define portMISSED_COUNTS_FACTOR ( 45UL )
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+#endif
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+
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+/* Let the user override the pre-loading of the initial LR with the address of
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+ * prvTaskExitError() in case it messes up unwinding of the stack in the
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+ * debugger. */
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+#ifdef configTASK_RETURN_ADDRESS
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+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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+#else
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+ #define portTASK_RETURN_ADDRESS prvTaskExitError
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+#endif
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+
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+/*
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+ * Setup the timer to generate the tick interrupts. The implementation in this
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+ * file is weak to allow application writers to change the timer used to
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+ * generate the tick interrupt.
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+ */
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+void vPortSetupTimerInterrupt( void );
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+
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+/*
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+ * Exception handlers.
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+ */
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+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
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+void xPortSysTickHandler( void );
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+void vPortSVCHandler( void );
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+
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+/*
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+ * Start first task is a separate function so it can be tested in isolation.
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+ */
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+static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
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+
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+/*
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+ * Used to catch tasks that attempt to return from their implementing function.
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+ */
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+static void prvTaskExitError( void );
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+
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+/*-----------------------------------------------------------*/
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+
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+/* Each task maintains its own interrupt status in the critical nesting
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+ * variable. */
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+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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+
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+/*-----------------------------------------------------------*/
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+
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+/*
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+ * The number of SysTick increments that make up one tick period.
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+ */
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+#if ( configUSE_TICKLESS_IDLE == 1 )
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+ static uint32_t ulTimerCountsForOneTick = 0;
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+#endif /* configUSE_TICKLESS_IDLE */
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+
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+/*
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+ * The maximum number of tick periods that can be suppressed is limited by the
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+ * 24 bit resolution of the SysTick timer.
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+ */
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+#if ( configUSE_TICKLESS_IDLE == 1 )
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+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
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+#endif /* configUSE_TICKLESS_IDLE */
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+
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+/*
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+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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+ * power functionality only.
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+ */
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+#if ( configUSE_TICKLESS_IDLE == 1 )
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+ static uint32_t ulStoppedTimerCompensation = 0;
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+#endif /* configUSE_TICKLESS_IDLE */
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+
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+/*-----------------------------------------------------------*/
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+
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+/*
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+ * See header file for description.
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+ */
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+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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+ TaskFunction_t pxCode,
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+ void * pvParameters )
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+{
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+ /* Simulate the stack frame as it would be created by a context switch
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+ * interrupt. */
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+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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+ pxTopOfStack--;
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+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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+ pxTopOfStack--;
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+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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+ pxTopOfStack -= 8; /* R11..R4. */
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+
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+ return pxTopOfStack;
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+}
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+/*-----------------------------------------------------------*/
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+
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+static void prvTaskExitError( void )
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+{
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+ volatile uint32_t ulDummy = 0UL;
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+
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+ /* A function that implements a task must not exit or attempt to return to
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+ * its caller as there is nothing to return to. If a task wants to exit it
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+ * should instead call vTaskDelete( NULL ).
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+ *
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+ * Artificially force an assert() to be triggered if configASSERT() is
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+ * defined, then stop here so application writers can catch the error. */
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+ configASSERT( uxCriticalNesting == ~0UL );
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+ portDISABLE_INTERRUPTS();
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+
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+ while( ulDummy == 0 )
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+ {
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+ /* This file calls prvTaskExitError() after the scheduler has been
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+ * started to remove a compiler warning about the function being defined
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+ * but never called. ulDummy is used purely to quieten other warnings
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+ * about code appearing after this function is called - making ulDummy
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+ * volatile makes the compiler think the function could return and
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+ * therefore not output an 'unreachable code' warning for code that appears
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+ * after it. */
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+ }
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortSVCHandler( void )
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+{
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+ /* This function is no longer used, but retained for backward
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+ * compatibility. */
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortStartFirstTask( void )
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+{
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+ /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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+ * table offset register that can be used to locate the initial stack value.
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+ * Not all M0 parts have the application vector table at address 0. */
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+ __asm volatile (
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+ " .syntax unified \n"
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+ " ldr r2, pxCurrentTCBConst2 \n"/* Obtain location of pxCurrentTCB. */
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+ " ldr r3, [r2] \n"
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+ " ldr r0, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */
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+ " adds r0, #32 \n"/* Discard everything up to r0. */
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+ " msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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+ " movs r0, #2 \n"/* Switch to the psp stack. */
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+ " msr CONTROL, r0 \n"
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+ " isb \n"
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+ " pop {r0-r5} \n"/* Pop the registers that are saved automatically. */
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+ " mov lr, r5 \n"/* lr is now in r5. */
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+ " pop {r3} \n"/* Return address is now in r3. */
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+ " pop {r2} \n"/* Pop and discard XPSR. */
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+ " cpsie i \n"/* The first task has its context and interrupts can be enabled. */
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+ " bx r3 \n"/* Finally, jump to the user defined task code. */
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+ " \n"
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+ " .align 4 \n"
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+ "pxCurrentTCBConst2: .word pxCurrentTCB "
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+ );
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+}
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+/*-----------------------------------------------------------*/
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+
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+/*
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+ * See header file for description.
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+ */
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+BaseType_t xPortStartScheduler( void )
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+{
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+ /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
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+ portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
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+ portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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+
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+ /* Start the timer that generates the tick ISR. Interrupts are disabled
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+ * here already. */
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+ vPortSetupTimerInterrupt();
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+
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+ /* Initialise the critical nesting count ready for the first task. */
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+ uxCriticalNesting = 0;
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+
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+ /* Start the first task. */
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+ vPortStartFirstTask();
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+
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+ /* Should never get here as the tasks will now be executing! Call the task
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+ * exit error function to prevent compiler warnings about a static function
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+ * not being called in the case that the application writer overrides this
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+ * functionality by defining configTASK_RETURN_ADDRESS. Call
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+ * vTaskSwitchContext() so link time optimisation does not remove the
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+ * symbol. */
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+ vTaskSwitchContext();
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+ prvTaskExitError();
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+
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+ /* Should not get here! */
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+ return 0;
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortEndScheduler( void )
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+{
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+ /* Not implemented in ports where there is nothing to return to.
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+ * Artificially force an assert. */
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+ configASSERT( uxCriticalNesting == 1000UL );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortYield( void )
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+{
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+ /* Set a PendSV to request a context switch. */
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+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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+
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+ /* Barriers are normally not required but do ensure the code is completely
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+ * within the specified behaviour for the architecture. */
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+ __asm volatile ( "dsb" ::: "memory" );
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+ __asm volatile ( "isb" );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortEnterCritical( void )
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+{
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+ portDISABLE_INTERRUPTS();
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+ uxCriticalNesting++;
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+ __asm volatile ( "dsb" ::: "memory" );
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+ __asm volatile ( "isb" );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vPortExitCritical( void )
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+{
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+ configASSERT( uxCriticalNesting );
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+ uxCriticalNesting--;
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+
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+ if( uxCriticalNesting == 0 )
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+ {
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+ portENABLE_INTERRUPTS();
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+ }
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+}
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+/*-----------------------------------------------------------*/
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+
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+uint32_t ulSetInterruptMaskFromISR( void )
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+{
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+ __asm volatile (
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+ " mrs r0, PRIMASK \n"
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+ " cpsid i \n"
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+ " bx lr "
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+ ::: "memory"
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+ );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
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+{
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+ __asm volatile (
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+ " msr PRIMASK, r0 \n"
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+ " bx lr "
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+ ::: "memory"
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+ );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void xPortPendSVHandler( void )
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+{
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+ /* This is a naked function. */
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+
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+ __asm volatile
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+ (
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+ " .syntax unified \n"
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+ " mrs r0, psp \n"
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+ " \n"
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+ " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */
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+ " ldr r2, [r3] \n"
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+ " \n"
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+ " subs r0, r0, #32 \n"/* Make space for the remaining low registers. */
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+ " str r0, [r2] \n"/* Save the new top of stack. */
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+ " stmia r0!, {r4-r7} \n"/* Store the low registers that are not saved automatically. */
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+ " mov r4, r8 \n"/* Store the high registers. */
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+ " mov r5, r9 \n"
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+ " mov r6, r10 \n"
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+ " mov r7, r11 \n"
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+ " stmia r0!, {r4-r7} \n"
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+ " \n"
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+ " push {r3, r14} \n"
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+ " cpsid i \n"
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+ " bl vTaskSwitchContext \n"
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+ " cpsie i \n"
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+ " pop {r2, r3} \n"/* lr goes in r3. r2 now holds tcb pointer. */
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+ " \n"
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+ " ldr r1, [r2] \n"
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+ " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */
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+ " adds r0, r0, #16 \n"/* Move to the high registers. */
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+ " ldmia r0!, {r4-r7} \n"/* Pop the high registers. */
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+ " mov r8, r4 \n"
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+ " mov r9, r5 \n"
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+ " mov r10, r6 \n"
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+ " mov r11, r7 \n"
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+ " \n"
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+ " msr psp, r0 \n"/* Remember the new top of stack for the task. */
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+ " \n"
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+ " subs r0, r0, #32 \n"/* Go back for the low registers that are not automatically restored. */
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+ " ldmia r0!, {r4-r7} \n"/* Pop low registers. */
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+ " \n"
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+ " bx r3 \n"
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+ " \n"
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+ " .align 4 \n"
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+ "pxCurrentTCBConst: .word pxCurrentTCB "
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+ );
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+}
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+/*-----------------------------------------------------------*/
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+
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+void xPortSysTickHandler( void )
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+{
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+ uint32_t ulPreviousMask;
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+
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+ ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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+ {
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+ /* Increment the RTOS tick. */
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+ if( xTaskIncrementTick() != pdFALSE )
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+ {
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+ /* Pend a context switch. */
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+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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+ }
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+ }
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+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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+}
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+/*-----------------------------------------------------------*/
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+
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+/*
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+ * Setup the systick timer to generate the tick interrupts at the required
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+ * frequency.
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+ */
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+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
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+{
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+ /* Calculate the constants required to configure the tick interrupt. */
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+ #if ( configUSE_TICKLESS_IDLE == 1 )
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+ {
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+ ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
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+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
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+ }
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+ #endif /* configUSE_TICKLESS_IDLE */
|
|
|
+
|
|
|
+ /* Stop and reset the SysTick. */
|
|
|
+ portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
|
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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|
|
+
|
|
|
+ /* Configure SysTick to interrupt at the requested rate. */
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
|
+ portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
|
|
|
+}
|
|
|
+/*-----------------------------------------------------------*/
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|
|
+
|
|
|
+#if ( configUSE_TICKLESS_IDLE == 1 )
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|
|
+
|
|
|
+ __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
|
|
|
+ {
|
|
|
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
|
|
|
+ TickType_t xModifiableIdleTime;
|
|
|
+
|
|
|
+ /* Make sure the SysTick reload value does not overflow the counter. */
|
|
|
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
|
|
|
+ {
|
|
|
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
|
|
|
+ * is accounted for as best it can be, but using the tickless mode will
|
|
|
+ * inevitably result in some tiny drift of the time maintained by the
|
|
|
+ * kernel with respect to calendar time. */
|
|
|
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
|
|
|
+
|
|
|
+ /* Calculate the reload value required to wait xExpectedIdleTime
|
|
|
+ * tick periods. -1 is used because this code will execute part way
|
|
|
+ * through one of the tick periods. */
|
|
|
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
|
|
|
+
|
|
|
+ if( ulReloadValue > ulStoppedTimerCompensation )
|
|
|
+ {
|
|
|
+ ulReloadValue -= ulStoppedTimerCompensation;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
|
|
|
+ * method as that will mask interrupts that should exit sleep mode. */
|
|
|
+ __asm volatile ( "cpsid i" ::: "memory" );
|
|
|
+ __asm volatile ( "dsb" );
|
|
|
+ __asm volatile ( "isb" );
|
|
|
+
|
|
|
+ /* If a context switch is pending or a task is waiting for the scheduler
|
|
|
+ * to be unsuspended then abandon the low power entry. */
|
|
|
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
|
|
|
+ {
|
|
|
+ /* Restart from whatever is left in the count register to complete
|
|
|
+ * this tick period. */
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
|
|
+
|
|
|
+ /* Restart SysTick. */
|
|
|
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
|
+
|
|
|
+ /* Reset the reload register to the value required for normal tick
|
|
|
+ * periods. */
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
|
|
+
|
|
|
+ /* Re-enable interrupts - see comments above the cpsid instruction()
|
|
|
+ * above. */
|
|
|
+ __asm volatile ( "cpsie i" ::: "memory" );
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Set the new reload value. */
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
|
|
|
+
|
|
|
+ /* Clear the SysTick count flag and set the count value back to
|
|
|
+ * zero. */
|
|
|
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
|
+
|
|
|
+ /* Restart SysTick. */
|
|
|
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
|
+
|
|
|
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
|
|
|
+ * set its parameter to 0 to indicate that its implementation contains
|
|
|
+ * its own wait for interrupt or wait for event instruction, and so wfi
|
|
|
+ * should not be executed again. However, the original expected idle
|
|
|
+ * time variable must remain unmodified, so a copy is taken. */
|
|
|
+ xModifiableIdleTime = xExpectedIdleTime;
|
|
|
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
|
|
|
+
|
|
|
+ if( xModifiableIdleTime > 0 )
|
|
|
+ {
|
|
|
+ __asm volatile ( "dsb" ::: "memory" );
|
|
|
+ __asm volatile ( "wfi" );
|
|
|
+ __asm volatile ( "isb" );
|
|
|
+ }
|
|
|
+
|
|
|
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
|
|
|
+
|
|
|
+ /* Re-enable interrupts to allow the interrupt that brought the MCU
|
|
|
+ * out of sleep mode to execute immediately. see comments above
|
|
|
+ * __disable_interrupt() call above. */
|
|
|
+ __asm volatile ( "cpsie i" ::: "memory" );
|
|
|
+ __asm volatile ( "dsb" );
|
|
|
+ __asm volatile ( "isb" );
|
|
|
+
|
|
|
+ /* Disable interrupts again because the clock is about to be stopped
|
|
|
+ * and interrupts that execute while the clock is stopped will increase
|
|
|
+ * any slippage between the time maintained by the RTOS and calendar
|
|
|
+ * time. */
|
|
|
+ __asm volatile ( "cpsid i" ::: "memory" );
|
|
|
+ __asm volatile ( "dsb" );
|
|
|
+ __asm volatile ( "isb" );
|
|
|
+
|
|
|
+ /* Disable the SysTick clock without reading the
|
|
|
+ * portNVIC_SYSTICK_CTRL_REG register to ensure the
|
|
|
+ * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
|
|
|
+ * the time the SysTick is stopped for is accounted for as best it can
|
|
|
+ * be, but using the tickless mode will inevitably result in some tiny
|
|
|
+ * drift of the time maintained by the kernel with respect to calendar
|
|
|
+ * time*/
|
|
|
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
|
|
|
+
|
|
|
+ /* Determine if the SysTick clock has already counted to zero and
|
|
|
+ * been set back to the current reload value (the reload back being
|
|
|
+ * correct for the entire expected idle time) or if the SysTick is yet
|
|
|
+ * to count to zero (in which case an interrupt other than the SysTick
|
|
|
+ * must have brought the system out of sleep mode). */
|
|
|
+ if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
|
|
|
+ {
|
|
|
+ uint32_t ulCalculatedLoadValue;
|
|
|
+
|
|
|
+ /* The tick interrupt is already pending, and the SysTick count
|
|
|
+ * reloaded with ulReloadValue. Reset the
|
|
|
+ * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
|
|
|
+ * period. */
|
|
|
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
|
|
|
+
|
|
|
+ /* Don't allow a tiny value, or values that have somehow
|
|
|
+ * underflowed because the post sleep hook did something
|
|
|
+ * that took too long. */
|
|
|
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
|
|
|
+ {
|
|
|
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
|
|
|
+ }
|
|
|
+
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
|
|
|
+
|
|
|
+ /* As the pending tick will be processed as soon as this
|
|
|
+ * function exits, the tick value maintained by the tick is stepped
|
|
|
+ * forward by one less than the time spent waiting. */
|
|
|
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Something other than the tick interrupt ended the sleep.
|
|
|
+ * Work out how long the sleep lasted rounded to complete tick
|
|
|
+ * periods (not the ulReload value which accounted for part
|
|
|
+ * ticks). */
|
|
|
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
|
|
|
+
|
|
|
+ /* How many complete tick periods passed while the processor
|
|
|
+ * was waiting? */
|
|
|
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
|
|
|
+
|
|
|
+ /* The reload value is set to whatever fraction of a single tick
|
|
|
+ * period remains. */
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
|
|
|
+ * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
|
|
|
+ * value. */
|
|
|
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
|
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
|
|
|
+ vTaskStepTick( ulCompleteTickPeriods );
|
|
|
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
|
|
|
+
|
|
|
+ /* Exit with interrpts enabled. */
|
|
|
+ __asm volatile ( "cpsie i" ::: "memory" );
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+#endif /* configUSE_TICKLESS_IDLE */
|
Wendal Chen